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When will the Cortex-R5 processor abandon normal memory accesses on receiving an interrupt?

Information in this article applies to:

  • Cortex-R5
  • Cortex-R4

Problem/Question

When will the Cortex-R5 processor abandon normal memory accesses on receiving an interrupt?

Scenario

When the Cortex-R5 is configured to use low interrupt latency mode, it is permitted to abandon and later restart transactions to normal memory locations. The transactions must complete successfully on the bus, but the data from the transactions will be discarded. The transaction will be re-issued after the interrupt handler has completed and the Cortex-R5 has resumed executing the previous code.

The same behavior applies to the Cortex-R4 processor.

Answer

Low interrupt latency

On receipt of an interrupt, the processor abandons any pending restartable memory operations. Restartable memory operations are the multiword transfer instructions LDM, LDRD, STRD, STM, PUSH, POP, and the Floating Point Unit multi-word memory access instructions that are accessing normal memory.

All other memory transactions are unaffected by the low interrupt latency feature. These memory transactions can be divided into two groups:

  • Memory accesses that are never abandoned and restarted, for example:

    • Accesses to device or strongly ordered memory regions

    • SWP instructions

    • Load and store exclusives

    • Memory accesses that might be abandoned and restarted.

The following accesses will sometimes be abandoned when an interrupt is received and restarted after the interrupt handler routine has completed:

  • Instruction fetches

  • All other memory access instructions to normal memory, including:

    • Single load or store transactions, for example LDR, LDRH, LDRB, STR, STRH, STRB, and single Floating Point Unit memory accesses

    • Coprocessor loads and stores

    • Miscellaneous memory accesses, for example SRS and RFE instructions

However, these transactions might need to complete before the interrupt is taken. These memory accesses are not controlled by the low interrupt latency feature. It is not possible to control whether these accesses are abandoned when an interrupt is received or if the access must complete before the interrupt is taken.

Workaround

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Example

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Related Information

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