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AXI guidelines for Cortex-M7

Information in this article applies to:

  • Cortex-M7
  • NIC-301 Network Interconnect
  • NIC-400 Network Interconnect


What are the guidelines for specifying the AXI slave interface to which you connect the AXIM master interface of the Cortex-M7?


This knowledge article is relevant to chip designers who are trying to integrate a Cortex-M7 processor with an AMBA AXI interconnect fabric.

The Arm Cortex-M7 processor has a single AXI master interface that is labeled AXIM. The AXIM interface is automatically configured as either a high-performance implementation or as an area optimized implementation. The configuration depends on the presence or absence of a level 1 data cache in the processor configuration.

The transaction-issuing capabilities of the AXIM interface are described in Arm documentation that is provided to chip designers. For the Cortex-M7 processor, the relevant information is in section 4.5.1 of the Cortex-M7 Integration and Implementation Manual (IIM).

In normal operation, the Cortex-M7 processor is unlikely to reach the maximum number of outstanding transactions. Good performance can probably be obtained even when the AXI master interface is connected to an AXI slave interface that has fewer capabilities than the maximum capabilities of the master.


For read transactions, Arm recommends that the AXI slave interface is configured to accept at least the following traffic:

  • One outstanding read on the ICU read ID 3’b100

  • One outstanding read on the LFB0 read ID 3’b010

  • One outstanding read on the LFB1 read ID 3’b011

  • Two outstanding reads on the LSU read ID 3’b000

For write transactions, the capabilities that are needed for good performance are more code-specific. You may need to run some representative code to form a clear understanding of what capabilities yield good performance. In general, performance will improve when the fabric supports more outstanding writes if you have either of the following:

  • more writes to one memory type

  • longer latency between write data and buffered response

For example, if your AXI write responses are sent back an average of N cycles after the final data element is sent out, then N+4 outstanding writes would be enough in most cases.





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