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What are the alignment requirements for M-profile vector extension memory access instructions?

Information in this article applies to:

  • M-profile

  • Cortex-M

Problem/Question

What are the alignment requirements for M-profile vector extension memory access instructions?

Scenario

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Answer

For Armv8-M main extensions and ArmV7-M, the unalignment memory access is supported in the scalar instructions LDR and STR.

For Armv8.1-M, the alignment requirement for the M-profile Vector Extension (MVE) vector memory access instructions is different. In short, unaligned MVE load or store accesses are not supported and cause an unaligned UsageFault exception.

There are three types of memory access instructions in the MVE:

  • Vector Load and Store instructions

    VLDR{B|H|W}.<dt> Qd, [Rn{, #+/-<imm>}]

    These instructions support a narrowing or widening operation. This means that the {B|H|W} and <dt> can be different in size. The alignment requirement for these instructions depends on the data type that is specified by {B|H|W}:

    • B needs byte alignment.

    • H needs two bytes alignment.

    • W needs four bytes alignment.

  • Vector Gather Load and Scatter Store instructions

    VLDR/VSTR{B|H|W|D}.<dt> Qd, [Rn, Qm]
    VLDR/VSTR{W|D}.<dt> Qd, [Qm{, #+/-<imm>}]

    These instructions support a narrowing or widening operation. This means that the {B|H|W} and <dt> can be different in size. The alignment requirement for these instructions depends on the data type that is specified by {B|H|W|D}:

    • B needs Byte alignment.

    • H needs two bytes alignment.

    • W needs four bytes alignment.

    • D needs four bytes alignment.

    The alignment for the vector Gather Load and Scatter Store instructions follows the same rule as the vector Load/Store instructions, apart from the only difference in the address mode.

    Note: All the elements of Qm must meet the final address alignment.

  • Vector Deinterleaving Load and Interleaving Store instructions

    VLDn/VSTn<pat>.<size> {Qd,…, Qd+(n-1)}, [Rn]<!>

    Unlike the preceding instructions, the Vector Deinterleaving Load and Interleaving Store instructions do not support the narrowing and widening operations. Therefore, the alignment requirement for the Vector Deinterleaving Load and Interleaving Store instructions depends on the memory data type that is specified by <size>:

    • 8 needs byte alignment.

    • 16 needs two-byte alignment.

    • 32 needs four-byte alignment.

Workaround

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Example

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Related Information

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