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1.1. Overview

The AMBA Test Interface Controller (TIC) is an ASB bus master that accepts test vectors from the external test bus (the 32-bit external data bus, if available) and initiates bus transfers. The TIC latches address vectors from the test bus and drives the ASB address bus.

Typically, the TIC is the highest priority AMBA bus master to ensure test access under all conditions.

This TIC model does not support control vector/address incrementing: that means that to change the address bus value, a specific address vector needs to be issued.

Figure 1.1. Test interface controller block diagram

Figure 1.1. Test interface controller block diagram

Figure 1.1 represents a TIC block in a system where the external 32-bit data bus becomes the test bus when performing test mode accesses. 16-bit and 8-bit data bus systems require, for example, 16 or 24 address lines to be reconfigured as bidirectional test port signals for test mode access. Such systems would use the TestMode signal to force the EBI into this state.

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