Request from the TIC, indicating that this master requires the bus. This signal must be set up to the falling edge of BCLK. The Arbiter should treat this signal as the highest priority request line (over and above any complex arbitration scheme it might support).
Grant signal that grants the bus to the test controller.
This active LOW signal indicates the reset status of the bus and is driven by the reset controller.
System (bus) clock. This clock times all bus transfers. The clock has two distinct phases—phase 1 in which BCLK is LOW and phase 2 in which BCLK is HIGH. In the example system this clock also operates in test mode as TCLK.
This signal indicates when current transfer will complete. This signal is valid on the rising edge of BCLK. It must be used in concert with the other slave response lines BERROR and BLAST.
This signal is used with BWAIT and BLAST to form the retract term in the bus master state machine.
This signal is used with BERROR and BWAIT to form the retract term.
Bus lock signal. The TIC does not support locked transfers. Since the TIC should be the highest priority master, its transfers should never be interrupted. Driven LOW when the TIC is granted.
These signals indicate the type of the next transaction, which in this master may be Address-only or Sequential. They are valid during the HIGH phase before the transfer to which they refer.
These signals indicate the size of the transfer, which for this master is always word (32 bits). These signals have the same timing as the address bus.
These signals deal with address location access protection control. When generated by the TIC, these signals indicate supervisor mode transfers. They have the same timing as the address bus.
System address bus. The addresses become valid during the HIGH phase before the transfer to which they refer and remain valid until the last HIGH phase of the transfer.
In test mode, the data bus is used to load values into the TIC’s address latch during “address vectors”. The TIC then drives the system address bus BA with this value during subsequent single/burst read-write vectors.
When HIGH, this signal indicates a write transfer and when LOW, a read. This signal has the same timing as the address bus.
Test request A. This signal is used, in combination with TREQB, to control access to the system bus from the test bus.
Test request B. This signal is used, in combination with TREQA, to control access to the system bus from the test bus.
Test Acknowledge. This signal is used to indicate that the test interface has been granted access to the system bus. It is also used to indicate transfer delays (ie. transfers with wait cycles).
This active LOW signal indicates that the EBI should drive TBUS onto DB.
This active LOW signal indicates that the EBI should drive its latched version of BD onto the external TBUS.
When low the BD latch in the EBI should be transparent.
Indicates that the test controller has taken control of the bus. It should be used to enable the external 32-bit test bus (for EBIs that need the TBUS to be specifically enabled) and to select the system clock source for test (TCLK).