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1.2. Hardware Interface and Signal Description

The Remap and Pause module is connected to the APB bus. Table 1.1 describes the APB signals used and produced.

APB signal descriptions
Name TypeSource/ DestinationDescription
PA In APB BridgeThis is the peripheral address bus, which is used by individual peripherals for decoding register accesses to that peripheral. The addresses become valid before PSTB goes HIGH and remain valid after PSTB goes LOW.
PD InOut APB Peripherals, BD busThis is the bidirectional peripheral data bus. The data bus is driven by this block during read cycles (when PWRITE is LOW).
PSTB In APB Bridge This strobe signal is used to time all accesses on the peripheral bus. The falling edge of PSTB is coincident with the falling edge of BCLK.
PWRITE In APB BridgeThis signal indicates a write to a peripheral when HIGH and a read from a peripheral when LOW. It has the same timing as the peripheral address bus. It becomes valid before PSTB goes HIGH and remains valid after PSTB goes LOW.
PSEL In APB BridgeWhen HIGH, this signal indicates that this module has been selected by the APB bridge. This selection is a decode of the system address bus. See the AMBA Peripheral Bus Controller for more details.
Pause Out APB peripherals/external worldPause signal. Module has entered Pause mode.
ReMap Out Memory Controller Remap. Output that indicates that the reset memory map is in operation.
NFIQ In Interrupt ControllerNFIQ interrupt input from the interrupt controller.
NIRQ In Interrupt ControllerNIRQ interrupt input from the interrupt controller.
BnRES In Reset Controller The active LOW bus reset signal.
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