This block contains two separate state machines, one to control the block when operating as a master, and one to control the read/write sequencing when it is functioning as a slave.
This block forces AREQ HIGH, so is continually requesting the bus—in normal operation this block would be the master controlling the bus.
To test this block, the test interface controller must obtain the bus and then address the block as a slave. The system decoder decodes the single memory location that the block occupies (using the DSELARM signal) and the block then appears as a single memory‑mapped register that can be written to and read from. This address is system dependent, so only the decoder need be changed if the system memory map is altered. The writes and reads to this block must be in a particular sequence, to allow the test vectors to be applied correctly. Accessing the block in this way will destroy the ARM state, unless action is taken to record the state and restore it after the test accesses.