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1.2. Hardware interface and signal description

Table 1.1 shows the top level connections to this block. These are the AMBA ASB signals, and are described further in the AMBA Specification (ARM IHI 0001). Figure 1.2 gives the basic timing for these signals.

Top level connections
NameTypeSource/destinationDescription
AGNTInArbiter

This is a signal from the bus arbiter which indicates that the bus master will be granted the bus when BWAIT is LOW. This signal changes during the LOW phase of BCLK and remains valid through the HIGH phase.

AREQOutArbiter

This signal indicates to the arbiter that this block requires the bus. In this module, this signal is permanently tied to Vdd by default, indicating that the ARM CPU requires the bus at all times. This signal must be set up to the falling edge of BCLK.

ARMNFIQInInterrupt controller

This is the active LOW ARM Fast Interrupt Request (nFIQ) signal. The interrupt controller muxes several interrupt sources, and produces ARMNFIQ. Typically there is only a single nFIQ signal in a system, although this may be disabled by the interrupt controller.

ARMNIRQInInterrupt controllerThis is the active LOW ARM Interrupt Request (nIRQ) signal. The interrupt controller muxes several interrupt sources, and produces ARMNIRQ.
BAOutCurrent bus master

This is the system address bus, which is driven by the current bus master. The address becomes valid during the BCLK HIGH phase before the transfer to which it refers, and remains valid until the last BCLK HIGH phase of the transfer.

BWRITEOutCurrent bus master

When HIGH this signal indicates a write cycle, when LOW a read cycle. This signal has the same timing as the address bus. It is driven by the bus master and becomes valid during the BCLK HIGH phase before the transfer to which it refers. It remains valid until the last BCLK HIGH phase of the transfer.

BCLKIn-

System (bus) clock. This clock times all bus transfers. The clock has two distinct phases: phase one in which BCLK is LOW and phase two in which BCLK is HIGH.

BD[31:0]In/OutBus master

This is the bidirectional system data bus. The data bus is driven by the current bus master during write transfers, and by this block during read transfers.

BWAITInSystem decoder and current bus master

This signal is driven by the selected bus slave to indicate if the current transfer may complete. If BWAIT is HIGH, a further bus cycle is required. If BWAIT is LOW the transfer may complete in the current bus cycle. When no bus transfer is taking place, this signal is driven by the system decoder. The selected bus slave drives this signal in the LOW phase of BCLK and is valid set up to the rising edge of BCLK.

BERRORInSystem decoder and current bus master

A transfer error is indicated by the selected bus slave using the BERROR signal. When BERROR is HIGH a transfer error has occurred, when BERROR is LOW, then the transfer is successful. This signal is also used in combination with the BLAST signal to indicate a bus retract operation. When no bus transfer is taking place, this signal is driven by the system decoder. The selected bus slave drives this signal in the LOW phase of BCLK and is valid set up to the rising edge of BCLK.

BLASTInSystem decoder and current bus master

This signal is driven by the selected bus slave to indicate if the current transfer should be the last of a burst sequence. When BLAST is HIGH the next bus transfer must allow for sufficient time for address decoding. When BLAST is LOW, the next transfer may continue a burst sequence. This signal is also used in combination with the BERROR signal to indicate a bus retract operation. When no bus transfer is taking place, this signal is driven by the bus decoder. The selected bus slave drives this signal in the LOW phase of BCLK and is valid set up to the rising edge of BCLK.

BLOKOutArbiter

When HIGH this signal indicates the following transfers are to be indivisible and no other bus master should be given access to the bus.This signal is driven by this block when granted and becomes valid during the BCLK HIGH phase before the transfer to which it refers. It remains valid until the last BCLK HIGH phase of the last locked transfer.

BPROT[1:0]OutDecoder, slaves

These signals provide additional information about a bus access and are primarily intended for use by a bus protection unit or by the system decoder. The signals indicate if the transfer is an opcode fetch or data access, as well as if the transfer is a supervisor mode access or user mode access. For the ARM710a this bus is fixed to “01”, indicating Supervisor data accesses. These signals have the same timing as the address bus. They are driven by the bus master and become valid during the BCLK HIGH phase before the transfer to which they refer, remaining valid until the last BCLK HIGH phase of the transfer.

BnRESInReset controller

This active LOW signal indicates the reset status of the bus and are driven by the reset controller.

BSIZE[1:0]OutCurrent bus master

These signals indicate the size of the transfer, which may be byte or word. AMBA allows halfword transfers, but the ARM710a does not support them. These signals have the same timing as the address bus. They are driven by this block when granted and become valid during the BCLK HIGH phase before the transfer to which they refer, remaining valid until the last BCLK HIGH phase of the transfer.

BTRAN[1:0]OutBus master

These signals indicate the type of the next transaction, which may be address-only, or sequential. AMBA supports non-sequential accesses, but the ARM710a never requests them.These signals are driven by the this block when AGNT is asserted and are valid during the BCLK HIGH phase before the transfer to which they refer.

DSELARMInSystem decoder

This is a signal from the bus decoder to a bus slave indicating that the slave device is selected and a data transfer is required. For this module, this signal is used to put the ARM core into a test mode so that vectors can be written in and out of the core. This signal becomes valid during the BCLK HIGH phase before the data transfer is required, and remains active until the last BCLK HIGH phase of the transfer.

Figure 1.2 shows the basic AMBA pipelined bus protocol, which is described further in the AMBA Specification (ARM IHI 0001).

Figure 1.2. Basic AMBA bus cycle

Figure 1.2. Basic AMBA bus cycle
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