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1.4.3. Timing Parameters

The timing parameters related to an ASB bus master operating in an AMBA system are also shown in textual form in the following two tables: Table 1.4 details the input signals; Table 1.5 details the output signals. Bi-directional signals can be found in both tables.

Bus master input timing parameters
ParameterDescription
TclklBCLK LOW time
TclkhBCLK HIGH time
TisnresBnRes de-asserted setup to rising BCLK
TihnresBnRes de-asserted hold after falling BCLK
TisrespBWAIT, BERROR and BLAST setup to rising BCLK
TihrespBWAIT, BERROR and BLAST hold after rising BCLK
TisdrFor read transfers, BD[31:0] setup to falling BCLK
TihdrFor read transfers, BD[31:0] hold after falling BCLK
TisagntAGNT setup to rising BCLK
TihagntAGNT hold after falling BCLK
Bus master output timing parameters
ParameterDescription
TovtrBTRAN valid after rising BCLK
TohtrBTRAN hold after falling BCLK
TovanFor Non-sequential transfers, BA[31:0] valid after rising BCLK
TovasFor Sequential transfers, BA[31:0] valid after rising BCLK
TovaaFor Address-only transfers, BA[31:0] valid after falling BCLK
TohaBA[31:0] hold after rising BCLK
TovctlnFor Non-sequential transfers,BWRITE, BSIZE[1:0] and BPROT[1:0] valid after rising BCLK
TovctlaFor Address-only transfers,BWRITE, BSIZE[1:0] and BPROT[1:0] valid after falling BCLK
TohctlBWRITE, BSIZE[1:0] and BPROT[1:0] hold after rising BCLK
TovdwnFor Non-sequential write transfers, BD[31:0] valid after risingBCLK
TovdwnFor Sequential write transfers, BD[31:0] valid after falling BCLK
TohdwFor write transfers, BD[31:0] hold after BCLK
TovlokBLOK valid after rising BCLK
TohlokBLOK hold after rising BCLK
TovareqAREQ valid after rising BCLK
TohareqAREQ hold after rising BCLK