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1.7.9. 1.7.10 FIFO DMA Request Delay (FDD)

The 8-bit FIFO DMA request delay (FDD) field is used to select the minimum number of memory controller clock cycles (half the frequency of the CPU clock) to wait between the servicing of each DMA request issued by the input FIFO. After a DMA request has completed, the value contained within FDD is loaded to a down counter that disables the input FIFO from issuing another DMA request until the counter decrements to zero. This counter ensures that the LCD’s DMA does not fully consume the bandwidth of the AMBA bus. Once the counter reaches zero, any pending or future DMA requests by the FIFO cause the DMA to arbitrate for the ARM system bus (ASB). Once the DMA burst cycle has completed, the process re-starts and the value in FDD is loaded to the counter to create another delay period: this disables the FIFO from issuing a DMA request. FDD can be programmed with a value that causes the FIFO to wait from 0–255 memory clock cycles after the completion of one DMA request and before the start of the next request. When FDD=0h00, the FIFO DMA request delay function is disabled. This function is only used for palette loading.

Table 1.9 shows the location of all seven bit-fields located in LCD control register (LcdControl). LcdEn is the only control bit that is reset to a known state, ensuring that the LCD is disabled after a reset of the LCD controller. The user must program all other control bit-fields before setting LcdEn=1 (a half-word or word write can be used to configure the whole register while setting LcdEn), and must also disable the LCD controller when changing the state of any control bit within the LCD controller.


Writes to reserved bits are ignored, and reads return zeros.

Figure 1.15. LCD control register LcdControl

Figure 1.15. LCD control register LcdControl
LCD control register LcdControl
0LcdEnLCD Controller Enable0 - LCD controller disabled1 - LCD controller enabled
1LcdBWLCD Monochrome0 - Color operation enabled1 - Monochrome operation enabled
2LcdDPLCD Dual-Panel0 - Single-panel display enabled, UPLcdData[3:0] used for monochrome, UPLcdData[7:0]used for color1 - Dual-panel display enabled, UPLcdData used for monochrome, UPLcdData andLPLcdData used for color
3DoneMaskDone Mask0 - Mask out the Frame Done (Done) Interrupt.1 - Mask not active.
4NextMaskNext Mask0 - Mask out the Next Frame (Next) Interrupt.1 - Mask not active
5ErrorMaskError Mask0 - Mask out the Bus Error Status (BER) Interrupt1 - Mask not active.
7LcdTFTLCD TFT0 - Passive or STN display operation enabled, dither logic is enabled1 - Active or TFT display operation enabled, external palette and DAC required, dither logicbypassed, pin timing changes to support continuous pixel clock, output enable, VSYNC,HSYNC signals
8LcdBELcd Big Endian0 - Little endian operation is selected, frame/pin buffer data is arranged into individual wordsof memory starting with the least significant nibble, byte or half-word1 - Big endian operation is selected, frame/pin buffer data is arranged into individual wordsof memory starting with the most significant nibble, byte or half-word

Mono 8 Bit Mode0 - UPLcdData[3:0] is used to output four pixel values to the upper panel each pixel clocktransition and UPLcdData[7:4] are used to output four pixel values to the lower panel ofeach pixel clock transition.1 - UPLcdData[7:0] is used to output eight pixel values to the upper panel of each pixelclock, and LPLcdData[7:0] is used to output eight pixel values to the lower panel of eachpixel clock


This bit is ignored in all other modes of operation except for single panel mode

19-12FDDFIFO DMA Request DelayEncoded value (0—255) used to specify the number of memory controller clocks. The inputFIFO DMA request should be disabled. The clock count starts after the last write of eachburst cycle. While the counter is decrementing, all DMA requests from the input FIFO aremasked. When the counter reaches zero, any pending or subsequent DMA requests areallowed to generate a four-word burst. Programming FDD=0h00 disables this function.