Palette RAM data and encoded pixel data is stored in off-chip memory (usually DRAM) in an area called the frame buffer. This data is transferred to the LCD controller’s 4-entry, 32- bit wide input FIFO and holding latch on a demand basis using the LCD controller’s dedicated DMA controller. The LCD controller has been placed on the ARM system bus (ASB) as a bus master rather than the ARM peripheral bus (APB) where all other peripherals are located, because it is a higher-speed synchronous bus that is able to maintain the data rate required for demanding displays such as dual-panel color. The LCD’s DMA contains two channels that transfer data from external memory to the input FIFO for LCD control mode. One channel is used for single-panel displays and two are used for dual-panel displays.
The LCD controller issues a service request to the DMA after it has been initialized and enabled. The DMA automatically performs four-word transfers, filling all but one entry of the FIFO. Values are taken from the bottom of the FIFO one entry at a time, and each 32-bit value is unpacked into individual pixel encodings that are 4, 8, 12 or 16 bits each. When enough entries are read from the FIFO, a service request is issued to the DMA.