The frame buffer is an area within off-chip memory that is used to supply enough encoded pixel values to fill the entire screen one or more times. At the start or lowest order address of the LCD controller’s frame buffer is a 32-byte buffer for 4- and 12-bit mode operation (512-byte buffer for all other modes of operation), used to store the look-up palette data for each frame. A 32-byte buffer is used to load the top 16 entries of the palette for 4, 12 and 16 bits-per-pixel encodings, and a 512-byte buffer is used to load the entire 256-entry palette for 8 bits-per-pixel encodings. Note that the palette is not used for 12 or 16 bits-per pixel encodings. The 32 bytes at the top of the frame buffer, however, must be zero-filled even though the data is not used. This is due to the fact that the bits-per-pixel must be loaded regardless of operation.
Each time a new frame is fetched from the frame buffer, the LCD controller’s palette is first loaded with data contained within the palette buffer. Each of the 256 palette entries is stored in adjacent half-words. Figure 1.6 show the palette entry organization for both little and big endian memory organization. The user may select how the LCD views the ordering of frame buffer palette/pixel entries by programming the Lcd Big Endian (LcdBE) bit in LCD control register (LcdControl). In little endian mode, palette entries are ordered starting with the least significant half-word followed by the most significant. In big endian mode, palette entries are arranged in an order starting with the most significant half-word followed by the least significant. Note that the ordering of the 4-bit R, G, B and mono pixel data (and the BPP field) does not change between little and big endian modes: only the relative positioning of the individual 16-bit palette entries changes.
The first palette entry (Palette Entry 0) also contains an extra field that is used to configure synchronously the LCD controller at the beginning of each frame. Bits 12 and 13 of the first palette entry contain a field that is used to select the number of bits-per-pixel that is to be used in the following frame and the number of entries that are used in the palette RAM. The bits-per-pixel (BPP) bit-field is decoded by the LCD to correctly unpack pixel data into nibbles, bytes, 12-bit values or half-words, and decoded by the palette to tell it how many address bits are contained in the pixel data it is supplied, configuring the palette size to 16 or 256 entries. Note that 12- and 16-bit pixel mode bypasses the LCD palette and supplies 12-bit values directly to the dither logic when passive mode is enabled, or 16-bit values directly to the output FIFOs when active mode is enabled. Table 1.6 shows the encoding of the BPP bit-field (in little endian mode).
00 - 4 bits-per-pixel
01 - 8 bits-per-pixel
1x - 12 bits-per-pixel in passive mode (LcdTFT=0), 16 bits-per-pixel in active mode (LcdTFT=1).
Note: Two 4-bit pixels are packed into each byte, and 12-bit pixels are right-justified on half-wordboundaries (in the same format as palette entry).
Following the palette buffer is the pixel data buffer that contains one encoded pixel value for each of the pixels present on the display. The number of pixel data values depends on the size of the screen (ie. 1024 x 768 = 786 432 encoded pixel values). Again, each pixel data value can be 4, 8 or 16 bits wide. Figures from Figure 1.7 through to Figure 1.10 show the memory organization (little endian mode) within the frame buffer for each size pixel encoding. Note that for 4-bit encodings, two pixels are placed into each byte, and for 12-bit encodings the value is right-justified within a half-word. These figures show the encoded pixel organization for little endian memory organization. Again, the user may select how the LCD views the ordering of frame buffer pixel entries by programming the Lcd Big Endian (LcdBE) bit in LCD control register. In big endian mode, pixel entries are arranged in an order starting with the most significant nibble, byte, or half-word and ending with the least significant.
In dual-panel mode, pixels are presented to two halves of the screen at the same time (upper and lower). A second DMA channel and input FIFO exists to support dual-panel operation. The DMA channels alternate service requests when filling the two input FIFOs. The palette buffer is implemented in DMA channel 1 but not channel 2, so the base address points to the top of the encoded pixel values for channel 2. The DMA controller contains a base and current address pointer register. The end address is calculated automatically by the LCD using display information such as pixels-per-line, lines per frame, single-/dualpanel mode, color/monochrome mode, and bits-per-pixel that are programmed by the user.
The LCD’s DMA may overshoot the end of the frame buffer by one burst cycle (4 word read). The LCD’s DMA reads these extra values but they are flushed from the input FIFO each time the frame clock is pulsed. The user must ensure that the four words immediately following the end of the frame buffer reside in legal memory space (ie. that do not cause a bus error if read). Since the LCD does not alter this memory (only reads are performed), these locations can be used for data storage unrelated to the LCD.
The equations below are used to calculate the total frame buffer size (in bytes) that should be programmed in the DMA, based on varying pixel size encodings and screen sizes. Note that for dual-panel mode the frame buffer size is equally distributed between the two DMA channels, and the DMA channel 2’s buffer is either 32 or 512 bytes smaller (no palette buffer).