Data from the LCD’s DMA is directed either to the palette or the input FIFO. The direction of data flow is switched whenever the LCD controller is first enabled by each frame pulse. After the LCD controller is configured and enabled, the first 32 or 512 bytes supplied by the DMA is sent to the palette. All subsequent encoded pixel data is sent to the FIFO. For passive mode displays the frame clock is pulsed at the beginning of the frame. This signal is also used to change the direction of DMA input data from the FIFO back to the palette. A modulus of 8 or 128 is used to count during loading of the palette RAM, depending on the pixel bit size shown above. A 7-bit counter is loaded each time a frame clock pulse occurs or the LCD is enabled. The counter is decremented each time a word is stored to the palette (that is, two palette entries). When the counter wraps around to zero, the data input from the DMA is switched back to the FIFO.
The LCD controller contains a 4-entry by 32-bit wide input FIFO and holding latch that is used to store encoded pixels fetched from the frame buffer. The FIFO signals a service request to the DMA whenever four entries of the FIFO are read. In turn, the DMA automatically fills the FIFO with a four-word blast.
Pixel data from the frame buffer remains packed within individual 32-bit words when it is loaded into the FIFO. The LCD controller’s port size is 32 bits wide to accommodate the heavy data flow from the frame buffer. Depending on the number of bits-per-pixel, as words are taken from the bottom of the FIFO they are unpacked and supplied to the look-up palette in either nibbles (4 bits/pixel) or bytes (8 bits/pixel), to the dither logic (12 bits/pixel), or directly to the pins in half-words (16 bits/pixel). When four entries are read, a service request is issued to the DMA.