For dual-panel mode, the pixels for the upper half of the screen are loaded to the least significant half of the LCD’s output FIFO shifter, and the pixels for the lower half are loaded to the most significant half of the shifter. When the shifter is filled, the value is driven to the LCD controller data bus pins (UpLcdData[3:0] for a 4-bit wide bus, to the UPLcdData for an 8-bit wide bus, and to the UPLcdData and LPLcdData for a 16-bit wide bus); in addition, the pixel clock pin (LcdCP) is toggled.
When an entire line of pixels has been output to the LCD screen, the line clock pin (LcdLP) is toggled. In the same manner, if the controller is in passive mode and when the start of the first line of a new frame of pixels has been output to the LCD controller screen, the frame clock pin (LcdFP) is toggled. To prevent a DC charge from building within the screen’s pixels, the display’s power and ground supplies are periodically switched. The LCD controller signals the display to switch the polarity by toggling the AC-bias pin (LcdAC). The user can control the frequency of the bias pin by programming the number of line clock transitions between each toggle.
When active display mode is enabled, the timing of the pixel, line and frame clocks as well as the AC-bias pin change. The pixel clock transitions continuously in this mode as long as the LCD is enabled. The AC-bias pin functions as an output enable. When it is asserted, the display latches data from the LCD’s pins using the pixel clock. The line clock pin is used as the horizontal synchronization signal (HSYNC), and the frame clock used as the vertical synchronization signal (VSYNC). See Figure 1.12.
The timing of the line and frame clock pins is programmable to support both passive and active mode. Programming options include:
delay insertion both at the beginning and end of each line and frame
pixel clock, line clock, frame clock and AC-bias signal polarity
line and frame clock pulse width.