The LCD controller contains a 19-entry by 16-bit wide output FIFO that is used to store pixel pin data before it is driven out to the pins. Each time a modulated pixel value is output from the dither generator it is placed into a serial shifter. The size of the shifter is controlled by programming the color/monochrome select and Lcd Dual Panel bits in the LCD’s control registers. The shifter can be configured to be 4, 8 or 16 bits wide. Single-panel monochrome screens use either four or eight data lines, single-panel color and dual-panel monochrome screens use eight data pins, and dual-panel color and active screens use 16 data pins. Once the correct number of pixels have been placed within the shifter (4-, 8- or 16-pixel values), the value is transferred to the top of the output FIFO. The value is then transferred down until it reaches the last empty location within the FIFO. As values reach the bottom of the FIFO, they are driven out one by one onto the LCD’s data pins on the edge selected by the Invert Pixel Clock (IPC) bit.