The Invert Output Enable (IEO) bit is used to select the active and inactive state of the output enable signal in active display mode. In this mode, the AC-bias pin is used as an enable that signals the off-chip device when data is actively being driven out using the pixel clock. When IEO=0, the LcdAC pin is active high. When IEO=1, the LcdAC pin is active low. In active display mode, data is driven onto the LCD’s data lines on the programmed edge of LcdCP when LcdAC is in its active state.
IEO does not affect LcdAC in passive display mode.
Table 1.12 shows the location of the seven different bit-fields located in LCD Timing 2 Register (LcdTiming2). The LCD controller must be disabled (LcdEn=0) when changing the state of any field within this register. The reset state of all bit-fields is unknown and must be initialized before enabling the LCD. Note that writes to reserved bits are ignored and reads return zeros.
|7–0||PCD||Pixel Clock DivisorValue (from 0–255) used to specify the frequency of the pixel clock based on the CPU clock(BCLK) frequency. Pixel clock frequency can range from BCLK/2 to BCLK/257.Pixel Clock Frequency = BCLK/2(PCD+2).Note that PCD must also be programmed in parallel data input mode to select the rate inwhich data is synchronously driven into and latched by the LCD controller.|
|15–8||ACB||AC Bias Pin FrequencyValue (from 0–255) used to specify the number of line clocks to count before transitioningthe AC Bias pin. This pin is used to periodically invert the polarity of the power supply toprevent DC charge build-up within the display.ACB = Number of line clocks/toggle of the LcdAC pin.|
|19–16||ACBI||AC Bias Pin Transitions per InterruptValue (from 0–255) used to specify the number of AC Bias pin transitions to count beforesetting the line count status (LCS) bit, signalling an interrupt request. Counter is frozen whenLCS is set, and is restarted when LCS is cleared by software. This function is disabled whenACBI=0x0000.|
|20||IVS||Invert Vsync0 - LcdFP pin is active high and inactive low.1 - LcdFP pin is active low and inactive high.Active mode: vertical sync pulse active between frames, after end of frame wait period.Passive mode: frame clock active during first line of each frame.|
|21||IHS||Invert Hsync0 - LcdLP pin is active high and inactive low.1 - LcdLP pin is active low and inactive high.Active and passive mode: horizontal sync pulse/line clock active between lines, after end ofline wait period.|
|22||IPC||Invert Pixel Clock0 - Data is driven on the LCD’s data lines on the rising-edge of LcdCP.1 - Data is driven on the LCD’s data lines on the falling-edge of LcdCP.|
|23||IEO||Invert Output Enable0 - LcdAC pin is active high in active display mode.1 - LcdAC pin is active low in active display mode.Active display mode: data driven out to the LCD’s data lines on programmed pixel clockedge when AC-bias is active. Note that IEO is ignored in passive display mode.|