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1.10.1. Pixel Clock Divider (PCD)

The 8-bit pixel clock divider (PCD) field is used to select the frequency of the pixel clock. PCD can generate a range of pixel clock frequencies from BCLK/2 to BCLK/257, where BCLK is the programmed frequency of the crystal clock. The pixel clock frequency should be adjusted to meet the required screen refresh rate. The refresh rate depends on:

  • the number of pixels for the target display

  • whether single- or dual-panel mode is selected

  • whether monochrome or color mode is selected

  • the number of pixel clock delays programmed at the beginning and end of each line

  • the number of line clocks inserted at the beginning and end of each frame

  • the width of the VSYNC signal in active mode or VSW line clocks inserted in passive mode

  • the width of the frame clock or HSYNC signal

All of these factors alter the time duration from one frame transmission to the next. Different display manufacturers require different frame refresh rates, depending on the physical characteristics of the display. PCD is used to alter the pixel clock frequency in order to meet these requirements. Note that PCD is also used in parallel data input mode to select the frequency of pixel clock. Pixel clock is used to synchronously signal the off-chip device to drive data to the LCD’s data pins, and to signal the output FIFO to latch the data from the pins. The frequency of the pixel clock for a set PCD value, or the required PCD value to yield a target pixel clock frequency can be calculated using the following equations:

Figure 1.20. Equations

Figure 1.20. Equations


For TFT mode, the minimum PCD is 2. For STN mode, the minimum PCD is 4 for mono 4 bit mode, 8 for mono 8 bit mode and 3 for color mode.

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