The LCD controller provides all the necessary control signals to interface directly to an ARM AMBA bus as a bus master controller. The LCD controller can operate in single-panel or dual-panel modes when connected to the associated multiplexed LCD. The block is designed to work with a separate RAM block to provide data to the FIFO at the front end of the LCD controller data path, at a rate sufficient to support the chosen display mode and resolution.
The panel size is programmable, and can be any width (line length) from 16 to 1024 pixels in 16-pixel increments. The number of lines is set by programming the total number of pixels in the LCD. The total video frame size is programmable up to 1024x1024; single- or dual-panel display mode is also supported.
The screen is intended to be mapped to the video buffer as one contiguous block where each horizontal line of pixels is mapped to a set of consecutive bytes of words in the video memory. The pixels stored in memory can be programmed and arranged in a little or big endian manner.
Assuming a bus clock frequency of 30MHz, the maximum screen resolution for this bandwidth would be 640x480 pixels. To display a resolution of 800x600 pixels, the bus clock frequency would have to be 50MHz.
The principal features of the LCD controller are:
encoded pixel data is stored in external memory in a frame buffer in 4-, 8- or 16-bit increments, and is loaded into a four-entry FIFO (32 bits per entry) and holding latch on a demand basis using the LCD’s own dedicated dual-channel DMA controller
programmable pixel display modes
programmable display size
16 grayscale levels
palette allowing full logical-to-physical address mapping
programmable pixel rate
four types of displays are supported—passive and active color, and passive and active monochrome
in passive STN mode a total of 3375 possible colors is available, allowing any 256 colors to be displayed in each frame, as well as 15 grayscale levels for monochrome screens
any screen size up to 1024x1024 (assuming big enough bandwidth) is supported, as well as single- or dual-panel display mode
frame, line and pixel clocks
AC-bias drive signal
4, 8 and 16 bit-per-pixel display modes
patented dithering algorithm
Frame buffer data contains encoded pixel values: these are used by the LCD controller as pointers to index into a 256-entry by 12-bit wide palette. Monochrome palette entries are 4bits wide, and color are 12 bits wide. Encoded pixel data from the frame buffer which is 4 bits wide addresses the first16 locations of the palette, and 8-bit pixel data accesses any of the 256 entries within the palette. When passive color 12-bit pixel mode is enabled, the color pixel values bypass the palette and are fed directly to the LCD’s dither logic. When active color 16-bit pixel mode is enabled, the pixel value not only bypasses the palette but also the dither logic, and is sent directly to the LCD’s data pins.
Once the 4- or 8-bit encoded pixel value is used to select a palette entry, the value programmed within the entry is transferred to the dither logic; this uses a patented space or time-based dithering algorithm to produce the pixel data that is output to the screen. Dithering causes individual pixels to be turned off and on in each frame at varying rates to produce the 15 levels of gray for monochrome screens, and 15 levels each for the red, green and blue pixel components for color screens: this provides a total of 3375 colors, 256 of which are available in each frame. The data output from the dither logic is placed in a FIFO before it is placed on the LCD’s pins and is driven to the display using the pixel clock.
Depending on the type of panel used, the LCD controller is programmed to use either 4-, 8- or 16-pixel data output pins. Single-panel monochrome displays use 4- or 8-bit data registers to output four or eight pixels respectively to each pixel clock, and single-panel color displays use eight pins to output 22/3 pixels to each pixel clock (8 pins / 3 colors/pixel = 22/3 pixels per clock). The LCD controller also supports dual-panel mode, which causes the LCD controller’s data lines to be split into two groups: one to drive the top half, and one to drive the bottom half of the screen. For dual-panel displays, the number of pixel data output pins are doubled, allowing twice as many pixels to be output from each pixel clock to the two halves of the screen.
In active (TFT) display mode, the LCD can be used with an external palette and DAC to drive a video monitor. The LCD’s line clock pin functions as a horizontal sync (HSYNC) signal and the frame clock pin functions as a vertical sync (VSYNC) signal. In TFT mode, the LCD’s dither logic is bypassed, sending selected palette entries directly to the LCD’s data output pins. Additionally, 16-bit pixels can be used, which bypass both the palette and the dither logic.
|BnRES||In||Reset Controller||The bus reset signal is active LOW and is used to reset the system and the bus.|
|BA[31:0]||InOut||Current Master/LCD||System address bus. The addresses become valid before the transfer to which they refer and remain valid until the last phase 2 of the transfer.|
|BCLK||In||AMBA Bus||The ASB clock, timing and all bus transfers. It has two distinct phases: phase 1 in which BCLK is LOW and phase 2 in which BCLK is HIGH.|
|BD[31:0]||InOut||Current Master,AMBA Bus||Bi-directional system data bus. The data bus is driven by the current bus master during write transfers and by this block during register read transfers.|
|BERROR||In||AMBA Bus||LCD slave signalling that a bus error has occurred.|
|BLAST||In||AMBA Bus||This signal is driven by the selected bus slave to indicate if the current transfer should be the last of a burst sequence. When BLAST is HIGH, the decoder must allow sufficient time for address decoding. When BLAST is LOW, the next transfer may continue a burst sequence. When no slave is selected, this signal is driven by the bus decode|
|BSIZE[1:0]||Out||Current Master||These signals indicate the size of the transfer, which may be byte, halfword or word. These signals have the same timing as the system address bus.|
|BWAIT||In||Current Master||Wait slave response signal. Driven in phase 1 when the DRAM controller is selected. Asserted while the DRAM transaction is incomplete.|
|BWRITE||InOut||Current Master||When HIGH this signal indicates a write transfer, and when LOW a read transfer. This signal has the same timing as the address bus.|
|BTRAN[1:0]||Out||Current Master||These signals are used to determine sequential and non-sequential accesses for RAM burst mode access control.|
|BPROT[1:0]||Out||Current Master||These signals indicate if the transfer is an opcode fetch of data access. The transfer will always be a supervisor mode.|
|UPLcdData||Out||DMA||Register used to store either four or eight data values at a time to the LCD display. For monochrome displays, each bit value represents a pixel; for passive color displays, groupings of three bit values represent one pixel (red, green and blue data values). UPLcdData[3:0] is used for single-panel monochrome displays; UPLcdData is used for dual-panel monochrome, as well as singlepanel color displays and active color modes.|
|LPLcdData||Out||DMA||When dual-panel color or TFT operation is programmed, LPLcdData is used as the additional, required LCD data register to output pixel data to the screen.|
|LcdCP||Out||LCD||Pixel clock used by the LCD display to clock the pixel data into the line shift register. In passive mode, pixel clock only transitions which valid data is available on the data lines. In active mode the pixel clock transitions continuously and the AC-bias pin is used as an output enable to signal when data is available on the LCD’s pins.|
|LcdLP||Out||LCD||Line clock used by the LCD display to signal the end of a line of pixels that transfers line data from the shift register to the screen, and to increment the line pointer(s). Also used by TFT displays as the horizontal synchronization signal.|
|LcdFP||Out||LCD||Frame clock used by the LCD displays to signal the start of a new frame of pixels. Also used by TFT displays as the vertical synchronization signal.|
|LcdAC||Out||LCD||AC-bias used to signal the LCD display to switch the polarity of the power supplies to the row and column axis of the screen to counteract DC offset. Used in TFT mode as the output enable to signal when data should be latched from the data pins using the pixel clock.|
The pixel clock frequency should be derived from the output of the on-chip PLL (BCLK) and is programmable from BCLK/2 to BCLK/257. Each time new data is supplied to the LCD data pins, the pixel clock is toggled to latch the data into the LCD display’s serial shifter. The line clock toggles after all pixels in a line have been transmitted to the LCD driver, and a programmable number of pixel clock wait states have elapsed both at the beginning and end of each line. In passive mode, the frame clock toggles during the first line of the screen, and the beginning and end of each frame is separated by a programmable number of line clock wait states (Horizontal Front Porch, HFP and Horizontal Back Porch, HBP should be programmed to zero in passive mode).
In active mode, the frame clock is asserted at the end of a frame after a programmable number of line clock wait states occur. In passive display mode, the pixel clock does not transition during wait state insertion or when the line clock is asserted. Finally, the AC-bias (LcdAC) can be configured to transition each time a programmable number of line clocks occurs.