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1.12. DMA Channel 1 Base Address Register

DMA channel 1 base address register (DBAR1) is a 32-bit register that is used to specify the base address of the off-chip frame buffer for DMA channel 1. The base address pointer register can be both read and written. Addresses programmed in the base address register must be aligned on word boundaries, thus the least significant two bits (DBAR1[1:0]) must always be written with zeros. The user must initialize the base address register before enabling the LCD, and may also write a new value to it while the LCD is enabled to allow a new frame buffer to be used for the next frame. The user can change the state of DBAR1 while the LCD controller is active just after the Next Frame (Next) status bit is set with the LCD’s status register that generates an interrupt request. This status bit indicates that the value in the base address pointer has transferred to the current address pointer register and that it is safe to write a new base address value. DMA channel 1 is used to transfer frame buffer data from off-chip memory to the LCD’s input FIFO and the palette RAM for single-panel mode, and for the top half of the screen in dual-panel mode.

Note

DBAR1 is not reset and must be initialized before enabling the LCD.

Figure 1.22. DMA channel 1 base address register DBAR1

Figure 1.22. DMA channel 1 base address register DBAR1
DMA channel 1 base address register DBAR1
BitNameDescription
31-0DBAR1DMA Channel 1 Base Address PointerUsed to specify the base address of the frame buffer within off-chip memory. Value inDBAR1 transferred to current address pointer register 1 when LCD is first enabled(LcdEN=1). DBAR1 should only be written when the LCD is disabled, or immediately afteran interrupt is generated by the setting of the Next Frame (Next) status bit. The baseaddress must be on a quad-word boundary, so the user must always write bits 0 and 1 tozero.
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