DMA channel 2’s base and current address registers function exactly like DMA channel 1’s except that they are used exclusively for dual-panel operation. Refer to DMA Channel 1 Base Address Register and DMA Channel 1 Current Address Register. When LcdDP=1, DMA channel 2 is used to supply frame buffer data to the lower half of the display.
The palette buffer that resides within the first 16 or 256 entries of the frame buffer is only utilized by DMA channel 1. The user should not place palette entries into the frame buffer for DMA channel 2. Thus the base address for channel 2 points to the first encoded pixel values for the lower half of the display.
|31-0||DBAR2||DMA Channel 2 Base Address PointerUsed to specify the base address of the frame buffer within off-chip memory for the lowerhalf of the display in dual-panel operation. Value in DBAR2 transferred to current addresspointer register 2 when LCD first enabled (LcdEN=1). DBAR2 should only be written whenthe LCD is disabled, or immediately after an interrupt is generated by the setting of the NextFrame (Next) status bit. The base address must be on a quad-word boundary, so the usermust always write bits 0 and 1 to zero.|
|31-0||DBAR2||DMA Channel 2 Current Address PointerRead-only register that continuously reflects the current address that DMA channel 2 istransferring from or will use in the next transfer. Base address register is transferred to thisregister whenever the LCD is enabled, or when the current address is equal to thecalculated end address of the buffer.|