The LCD controller contains four control registers, four DMA address registers and one status register. The control registers contain bit-fields to enable and disable the LCD controller to define:
the height and width of the screen being controlled
single- or dual-panel display mode
color or monochrome mode
passive or active display
polarity of the control lines
pulse width of the line and frame clocks
the pixel clock and AC-bias frequency
the number of delays to insert before/after each line and after each frame.
An additional control field exists to tune the DMA’s performance, based on the type of memory system in which the LCD controller is used. This field controls the placement of a minimum delay between each LCD palette request to ensure enough bus bandwidth is given to other ARM systems’ bus masters for access. This field is only used for palette load.
The DMA address registers are used to define the base address of the off-chip frame buffer as well as to which address the DMA is currently pointing. Both of these registers exist for DMA channel 1 and 2.
The status registers contain bits that signal:
FIFO underrun error
DMA bus errors
when the DMA base address can be re-programmed
when the last active frame has completed after the LCD is disabled
Each of these hardware-detected events signal an interrupt request to the interrupt controller.