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1.9.4. Vertical Back Porch (VBP)

The 8-bit Vertical Back Porch (VBP) field is used to specify the number of line clocks to insert at the beginning of each frame. The VBP count starts just after the VSYNC signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit-field in passive mode. After this has occurred, the value in VBP is used to count the number of line clock periods to insert before starting to output pixels in the next frame. VBP generates from 0–255 extra line clock cycles (program to value required minus one).

Note

The line clock pin LcdLP transitions during the generation of the VBP line clock wait periods. Note also that the user should adjust the value of VBP appropriately such that enough line clock cycles are permitted to elapse: this allows the on-chip palette to be completely filled via the DMA, and allows a sufficient number of encoded pixel values to be input from the frame buffer, processed by the dither logic then placed in the output FIFO, ready to be output to the LCD’s data lines.

See Figure 1.18.

Figure 1.18. Passive mode beginning of frame timing

Figure 1.18. Passive mode beginning of frame timing

Table 1.11 shows the location of the four bit-fields located in LCD Timing 1 Register (LcdTiming1). The LCD controller must be disabled (LcdEn=0) when changing the state of any field within this register. The reset state of all bitfields is unknown and must be initialized before enabling the LCD.

Figure 1.19. LCD Timing 1 Register (LcdTiming1)

Figure 1.19. LCD Timing 1 Register (LcdTiming1)
LCD Timing 1 Register (LcdTiming1)
BitNameDescription
9-0LPPLines Per PanelValue (from 1–1024) used to specify number of lines per panel. For single-panel mode, thisrepresents the total number of lines on the LCD display; for dual-panel mode, thisrepresents half the number of lines on the whole LCD display.
15-10VSWVertical Sync Pulse WidthIn active mode (LcdTFT=1), value (from 0–63) used to specify number of line clock periodsto pulse the LcdFP pin at the end of each frame after the end of frame wait (VFP) periodelapses. Frame clock used as VSYNC signal in active mode.In passive mode (LcdTFT=0), value (from 0–63) used to specify number of extra line clockperiods to insert after the vertical front porch (VFP) period has elapsed. Note that the widthof LcdFP is not effected by VSW in passive mode, and that line clock transitions during theinsertion of the extra line clock periods.
23-16VFPVertical Front PorchValue (from 0–255) used to specify number of line clock periods to add to the end of eachframe. Note that the line clock transitions during the insertion of the extra line clock periods.
31-24VBPVertical Back PorchValue (from 0–255) used to specify number of line clock periods to add to the beginning of aframe before the first set of pixels is output to the display. Note that line clock transitions duringthe insertion of the extra line clock periods.
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