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A.1. Instruction memory interface signals

Instruction memory interface signals

Name

Direction

Description

IA[31:1]

Output

Instruction Address Bus. This is the processor instruction address bus. It changes when GCLK is HIGH.

IABE

Input

Instruction Address Bus Enable. This is an input which, when LOW, it puts the instruction address bus, IA[31:0], drivers into a high impedance state. This signal has the same effect on InTRANS and InM[4:0].

If UNIEN is HIGH this signal is ignored.

IABORT

Input

Instruction Abort. This is an input which allows the memory system to tell the processor that the requested instruction memory access is not allowed.

ID[31:0]

Input

Instruction Data Bus. This input bus should be driven with the requested instruction data before the end of phase 2 of GCLK.

InM[4:0]

Output

Instruction Mode. These signals indicate the current mode of the processor and are in the same form as the mode bits in the CPSR.

InMREQ

Output

Not Instruction Memory Request.

If LOW at the end of GCLK phase 2, the processor requires an instruction memory access during the following cycle.

InTRANS

Output

Not Memory Translate.

When LOW, the processor is in user mode.

When HIGH, the processor is in a privileged mode.

ISEQ

Output

Instruction Sequential Address. If HIGH at the end of GCLK phase 2, any instruction memory access during the following cycle is sequential from the last instruction memory access.

ITBIT

Output

Instruction Thumb Bit.

When HIGH, the processor is in Thumb state.

When LOW, the processor is in ARM state.

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