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A.2. Data memory interface signals

Data memory interface signals

Name

Direction

Description

DA[31:0]

Output

Data Address Bus. This is the processor data address bus. It changes when GCLK is HIGH.

DABE

Input

Data Address Bus Enable. When LOW, this input puts the data address bus, DA[31:0], drivers into a high impedance state. This signal has the same effect on DnTRANS, DLOCK, DMAS[1:0], DnRW, and DnM[4:0]. If UNIEN is HIGH this signal is ignored.

DABORT

Input

Data Abort. This input allows the memory system to tell the processor that the requested data memory access is not allowed.

DD[31:0]

Output

Data Output Bus. This output bus is used to transfer write data between the processor and external memory. The output data will become valid during phase 1 and remain valid through GCLK phase 2.

If UNIEN is LOW, this is a tristate output bus and is only driven during write cycles.

If UNIEN is HIGH, this bus is always driven.

DDBE

Input

Data Data Bus Enable. This is an input which, when LOW, puts the Data Data Bus DD[31:0] into a high impedance state. If UNIEN is HIGH this signal is ignored.

DDEN

Output

Data Data Bus Output Enabled. This signal indicates when the processor is performing a write transfer on the Data Data Bus, DD[31:0].

DDIN[31:0]

Input

Data Input Bus. This input is used to transfer load data between external memory and the processor. It should be driven with the requested data by the end of GCLK phase 2.

DLOCK

Output

Data Lock. If HIGH at the end of GCLK phase 2, any data memory access in the following cycle is locked, and the memory controller must wait until DLOCK goes LOW before allowing another device to access memory.

DMAS[1:0]

Output

Data Memory Access Size. These outputs encode the size of a data memory access in the following cycle. A word access is encoded as 10 (binary), a halfword access as 01, and a byte access as 00. The encoding 11 is reserved.

DMORE

Output

Data More. If HIGH at the end of GCLK phase 2, the data memory access in the following cycle will be directly followed by a sequential data memory access.

DnM[4:0]

Output

Data Mode. The processor mode within which the data memory access should be performed.

Note that the data memory access mode may differ from the current processor mode.

DnMREQ

Output

Not Data Memory Request. If LOW at the end of GCLK phase 2, the processor requires a data memory access in the following cycle.

DnRW

Output

Data not Read, Write.

If LOW at the end of phase 2, any data memory access in the following cycle is a read.

If HIGH, it is a write.

DnTRANS

Output

Data Not Memory Translate. If LOW, the next data memory access is to be performed as a user mode access, if HIGH the data memory access is to performed as a privileged mode access.

Note that the data memory access mode may differ from the current processor mode.

DSEQ

Output

Data Sequential Address. If HIGH at the end of phase 2, any data memory access in the next cycle is sequential from the current data memory access.

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