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A.4. JTAG and TAP controller signals

JTAG and TAP controller signals

Name

Direction

Description

DRIVEOUTBS

Output

Boundary Scan Cell Enable. This signal is used to control the multiplexers in the scan cells of an external boundary scan chain. This signal changes in the UPDATE‑IR state when scan chain 3 is selected and either the INTEST, EXTEST, CLAMP or CLAMPZ instruction is loaded. When an external boundary scan chain is not connected, this output should be left unconnected.

ECAPCLKBS

Output

Extest Capture Clock for Boundary Scan. This is a TCK2 wide pulse generated when the TAP controller state machine is in the CAPTURE-DR state, the current instruction is EXTEST and scan chain 3 is selected. This signal is used to capture the chip level inputs during EXTEST. When an external boundary scan chain is not connected, this output should be left unconnected.

ICAPCLKBS

Output

Intest Capture Clock. This is a TCK2 wide pulse generated when the TAP controller state machine is in the CAPTURE-DR state, the current instruction is INTEST and scan chain 3 is selected. This signal is used to capture the chip level outputs during INTEST. When an external boundary scan chain is not connected, this output should be left unconnected.

IR[3:0]

Output

Tap Controller Instruction Register. These four bits reflect the current instruction loaded into the TAP controller instruction register. The bits change on the falling edge of TCK when the state machine is in the UPDATE-IR state.

PCLKBS

Output

Boundary Scan Update Clock. This is a TCK2 wide pulse generated when the TAP controller state machine is in the UPDATE-DR state and scan chain 3 is selected. This signal is used by an external boundary scan chain as the update clock. When an external boundary scan chain is not connected, this output should be left unconnected.

RSTCLKBS

Output

Boundary Scan Reset Clock. This signal denotes that either the TAP controller state machine is in the RESET state, or that nTRST has been asserted. This may be used to reset external boundary scan cells.

SCREG[4:0]

Output

Scan Chain Register. These four bits reflect the ID number of the scan chain currently selected by the TAP controller. These bits change on the falling edge of TCK when the TAP state machine is in the UPDATE-DR state.

SDIN

Output

Boundary Scan Serial Input Data. This signal contains the serial data to be applied to an external scan chain, and is valid around the falling edge of TCK.

SDOUTBS

Input

Boundary Scan Serial Output Data. This is the serial data out of the boundary scan chain (or other external scan chain). It should be set up to the rising edge of TCK. When an external boundary scan chain is not connected, this input should be tied LOW.

SHCLK1BS

Output

Boundary Scan Shift Clock Phase 1. This control signal is provided to ease the connection of an external boundary scan chain. SHCLK1BS is used to clock the master half of the external scan cells. When the state machine is in SHIFT-DR state, scan chain 3 is selected, SHCLK1BS follows TCK1. When not in the SHIFT-DR state, or when scan chain 3 is not selected, this clock is LOW. When an external boundary scan chain is not connected, this output must be left unconnected.

SHCLK2BS

Output

Boundary Scan Shift Clock Phase 2. This control signal is provided to ease the connection of an external boundary scan chain. SHCLK2BS is used to clock the slave half of the external scan cells. When the state machine is in SHIFT-DR state, scan chain 3 is selected, SHCLK2BS follows TCK2. When not in the SHIFT-DR state, or when scan chain 3 is not selected, this clock is LOW. When an external boundary scan chain is not connected, this output must be left unconnected.

TAPID[31:0]

Input

TAP Identification. The value on this bus will be captured when using the IDCODE instruction on the TAP controller state machine.

TAPSM[3:0]

Output

TAP Controller State Machine. This bus reflects the current state of the TAP controller state machine. These bits change off the rising edge of TCK.

TCK

Input

The JTAG clock (the test clock).

TCK1

Output

TCK, Phase 1. TCK1 is HIGH when TCK is HIGH, although there is a slight phase lag due to the internal clock non-overlap.

TCK2

Output

TCK, Phase 2. TCK2 is HIGH when TCK is LOW, although there is a slight phase lag due to the internal clock non-overlap.

TDI

Input

Test Data Input, the JTAG serial input.

TDO

Output

Test Data Output, the JTAG serial output.

nTDOEN

Output

Not TDO Enable. When LOW, this signal denotes that serial data is being driven out on the TDO output. The nTDOEN signal would normally be used as an output enable for a TDO pin in a packaged part.

TMS

Input

Test Mode Select. TMS selects to which state the TAP controller state machine should change.

nTRST

Input

Not Test Reset. Active-low reset signal for the boundary scan logic. This pin must be pulsed or driven LOW after power up to achieve normal device operation, in addition to the normal device reset (nRESET).

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