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A.5. Debug signals

Debug signals

Name

Direction

Description

COMMRX

Output

Communications Channel Receive. When HIGH, this signal denotes that the comms channel receive buffer contains data waiting to be read by the ARM9TDMI.

COMMTX

Output

Communications Channel Transmit. When HIGH, this signal denotes that the comms channel transmit buffer is empty and the ARM9TDMI can write new data to the comms channel.

DBGACK

Output

Debug Acknowledge. When HIGH, this signal indicates the ARM9TDMI is in debug state.

DBGEN

Input

Debug Enable. This input signal allows the debug features of the ARM9TDMI to be disabled. This signal should be LOW only when debugging will not be required.

DBGRQI

Output

Internal Debug Request. This signal represents the debug request signal which is presented to the processor core. This is a combination of EDBGRQ, as presented to the ARM9TDMI, and bit 1 of the debug control register.

DEWPT

Input

Data Watchpoint. This is an input which allows external hardware to halt execution of the processor for debug purposes. If HIGH at the end of phase 1 following a data memory request cycle, it will cause the ARM9TDMI to enter debug state.

EDBGRQ

Input

External Debug Request. When driven HIGH, this causes the processor to enter debug state after execution of the current instruction completes.

EXTERN0

Input

External Input 0. This is an input to watchpoint unit 0 of the EmbeddedICE macrocell in the processor which allows breakpoints/watchpoints to be dependent on an external condition.

EXTERN1

Input

External Input 1. This is an input to watchpoint unit 1 of the EmbeddedICE macrocell in the processor which allows breakpoints/watchpoints to be dependent on an external condition.

IEBKPT

Input

Instruction Breakpoint. This is an input which allows a external hardware to halt the execution of the processor for debug purposes. If HIGH at the end of phase 1 following an instruction memory request cycle, it causes the ARM9TDMI to enter debug state if the relevant instruction reaches the execute stage of the processor pipeline.

INSTREXEC

Output

Instruction Executed. Indicates that in the previous cycle the instruction in the execute stage of the pipeline passed its condition codes, and was executed.

RANGEOUT0

Output

EmbeddedICE Rangeout 0. This signal indicates that the EmbeddedICE macrocell watchpoint unit 0 has matched the conditions currently present on the address, data and control buses. This signal is independent of the state of the watchpoint’s enable control bit.

RANGEOUT1

Output

EmbeddedICE Rangeout 1. This signal indicates that the EmbeddedICE macrocell watchpoint unit 1 has matched the conditions currently present on the address, data and control buses. This signal is independent of the state of the watchpoint’s enable control bit.

TBE

Input

Test Bus Enable. When driven LOW, TBE forces the following signals to HIGH impedance:

DD[31:0]

DA[31:0]

DLOCK

DMAS[1:0]

DnM[4:0]

DnRW

DnTRANS

DMORE

DnMREQ

DSEQ

IA[31:0]

InM[4:0]

InTRANS

InMREQ

ISEQ

ITBIT

LATECANCEL

PASS.

Under normal operating conditions, TBE should be held HIGH at all times.

If UNIEN is HIGH, this signal is ignored.

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