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A.6. Miscellaneous signals

Miscellaneous signals

Name

Direction

Description

BIGEND

Input

Big-Endian Configuration.

When this input is HIGH, the ARM9TDMI processor treats bytes in memory as being in big-endian format. When it is LOW, memory is treated as little-endian.

ECLK

Output

External Clock.

The clock by which the ARM9TDMI is currently being clocked. This clock will reflect any wait states applied by nWAIT, and once debug state has been entered by the debug clock.

nFIQ

Input

Not Fast Interrupt request.

This input causes the core to be interrupted if taken LOW, and if the appropriate enable in the processor is active. The signal is level-sensitive and must be held LOW until a suitable response is received from the processor. The nFIQ signal may be synchronous or asynchronous, depending on the state of ISYNC.

GCLK

Input

Clock.

This clock times all ARM9TDMI memory accesses (both data and instruction), and internal operations. The clock has two distinct phases—phase 1 in which GCLK is LOW and phase 2 in which GCLK is HIGH. The clock may be stretched indefinitely in either phase to allow access to slow peripherals or memory. Alternatively, nWAIT may be used with a free running GCLK to stretch phase 2.

HIVECS

Input

High Vectors Configuration.

When LOW, the ARM9TDMI exception vectors start at address 0x00000000 (hexadecimal). When HIGH, the ARM9TDMI exception vectors start at address 0xFFFF0000.

nIRQ

Input

Not Interrupt Request.

As nFIQ, but with lower priority. May be taken LOW to interrupt the processor when the appropriate enable is active. The nIRQ signal may be synchronous or asynchronous, depending on the state of ISYNC.

ISYNC

Input

Synchronous Interrupts.

When LOW, this input indicates that the nIRQ and nFIQ inputs are to be synchronized by the processor. When HIGH it disables this synchronization for inputs that are already synchronous.

nRESET

Input

Not Reset.

This is a level‑sensitive input signal which is used to start the processor from a known address. The ARM9TDMI processor asynchronously enters reset when nRESET goes LOW.

nWAIT

Input

Not Wait.

When a memory request cannot be processed in a single cycle, the ARM9TDMI can be made to wait for a number of GCLK cycles by driving nWAIT LOW. Internally, the inverse of nWAIT is ORed with GCLK, and must only change when GCLK is HIGH. If nWAIT is not used, it must be tied HIGH.

UNIEN

Input

Unidirectional Enable.

When HIGH, all ARM9TDMI outputs are permanently driven, (the state of IABE, DABE, DDBE and TBE is ignored). The DDIN[31:0] and DD[31:0] buses form a unidirectional data bus.

When LOW, outputs can go tristate and the DD[31:0] bus is only driven during write cycles. If DD[31:0] and DDIN[31:0] are wired together, they form a bidirectional data bus.

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