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8.2. ARM9TDMI timing parameters


ARM9TDMI timing parameters

Timing parameter

Description

Tbigh

BIGEND hold time from GCLK falling

Tbigs

BIGEND setup time to GCLK falling

Tbrst

Delay from nTRST falling to RSTCLKBS rising

Tbrtd

RSTCLKBS rising from TCK falling

Tbrth

RSTCLKBS falling from TCK rising

Tcapf

ECAPCLKBS/ICAPCLKBS/PCLKBS falling from TCK rising

Tcaph

Input hold time to TCK falling (EXTEST capture)

Tcapr

ECAPCLKBS/ICAPCLKBS/PCLKBS rising from TCK falling

Tcaps

Input setup time to TCK falling (EXTEST capture)

Tchsh

CHSD[1:0]/CHSE[1:0] hold time from GCLK falling

Tchss

CHSD[1:0]/CHSE[1:0] setup time to GCLK falling

Tcomd

COMMTX/COMMRX output delay

Tcomh

COMMTX/COMMRX output hold time

Tdabe

Delay from DABE rising to DA[31:0]/DnTRANS/DnM[4:0]/DMAS[1:0]/DnRW/DLOCK driven valid

Tdabh

DABORT hold time from GCLK falling

Tdabs

DABORT setup time to GCLK falling

Tdabtd

DnMREQ delay from DABORT

Tdabz

Delay from DABE falling to DA[31:0]/DnTRANS/DnM[4:0]/DMAS[1:0]/DnRW/DLOCK high impedance

Tdad

DA[31:0] delay from GCLK rising

Tdah

DA[31:0] hold time from GCLK rising

Tdbqh

EDBGRQ input hold time from GCLK falling

Tdbqs

EDBGRQ input setup time to GCLK falling

Tdckd

DBGACK output delay

Tdckh

DBGACK output hold time

Tddbe

Delay from DDBE rising to DD[31:0] (output) driven valid

Tddbz

Delay from DDBE falling to DD[31:0] (output) high impedance

Tddend

DDEN delay from GCLK falling

Tddenh

DDEN hold time from GCLK falling

Tddh

DD[31:0] (input) hold time from GCLK falling

Tddod

DD[31:0] (output) delay from GCLK falling

Tddoh

DD[31:0] (output) hold time from GCLK falling

Tdds

DD[31:0] (input) setup time to GCLK falling

Tdgid

DBGRQI output delay from TCK falling

Tdgih

DBGRQI output hold time from TCK falling

Tdih

TDI and TMS hold time from TCK rising

Tdis

TDI and TMS setup time to TCK rising

Tdlkd

DLOCK delay from GCLK rising

Tdlkh

DLOCK hold time from GCLK rising

Tdmqd

DnMREQ delay from GCLK rising

Tdmqh

DnMREQ hold time from GCLK rising

Tdmrd

DMORE delay from GCLK rising

Tdmrh

DMORE hold time from GCLK rising

Tdmsd

DMAS[1:0] delay from GCLK rising

Tdmsh

DMAS[1:0] hold time from GCLK rising

Tdnmd

DnM[4:0] delay from GCLK rising

Tdnmh

DnM[4:0] hold time from GCLK rising

Tdqen

DBGRQI falling delay from DBGEN falling

Tdqir

nTRST falling to DBGRQI falling delay

Tdrbsd

DRIVEOUTBS delay from TCK falling

Tdrbsh

DRIVEOUTBS hold time from TCK falling

Tdrwd

DnRW delay from GCLK rising

Tdrwh

DnRW hold time from GCLK rising

Tdsqd

DSEQ delay from GCLK rising

Tdsqh

DSEQ hold time from GCLK rising

Tdtrsd

DnTRANS delay from GCLK rising

Tdtrsh

DnTRANS hold time from GCLK rising

Tdwph

DEWPT hold time from GCLK rising

Tdwps

DEWPT setup time to GCLK rising

Tedqd

DBGRQI output delay from EDBGRQ changing

Tedqh

DBGRQI output hold time from EDBGRQ changing

Texth

EXTERN0/EXTERN1 input hold time from GCLK falling

Texts

EXTERN0/EXTERN1 input setup time to GCLK falling

Tgclkh

Minimum GCLK HIGH period

Tgclkl

Minimum GCLK LOW period

Tgekf

GCLK falling to ECLK falling delay

Tgekr

GCLK rising to ECLK rising delay

Thivh

HIVECS hold time from GCLK rising

Thivs

HIVECS setup time to GCLK rising

Tiabe

Delay from IABE rising to IA[31:1]/InM[4:0]/InTRANS driven valid

Tiabh

IABORT hold time from GCLK falling

Tiabs

IABORT setup time to GCLK falling

Tiabz

Delay from IABE falling to IA[31:1]/InM[4:0]/InTRANS high impedance

Tiad

IA[31:1] delay from GCLK rising

Tiah

IA[31:1] hold time from GCLK rising

Tibkh

IEBKPT hold time from GCLK rising

Tibks

IEBKPT setup time to GCLK rising

Tidh

ID[31:0] hold time from GCLK falling

Tids

ID[31:0] setup time to GCLK falling

Timqd

InMREQ delay from GCLK rising

Timqh

InMREQ hold time from GCLK rising

Tinmd

InM[4:0] delay from GCLK rising

Tinmh

InM[4:0] hold time from GCLK rising

Tinth

Interrupt (nFIQ/nIRQ) hold time from GCLK falling

Tints

Interrupt (nFIQ/nIRQ) setup time to GCLK falling

Tinxd

INSTREXEC output delay

Tinxh

INSTREXEC output hold time

Tirsd

IREG[3:0]/SCREG[4:0] output delay from TCK falling

Tirsh

IREG[3:0]/SCREG[4:0] hold time from TCK falling

Tisqd

ISEQ delay from GCLK rising

Tisqh

ISEQ hold time from GCLK rising

Tisyh

ISYNC hold time from GCLK falling

Tisys

ISYNC setup time to GCLK falling

Titbd

ITBIT delay from GCLK rising

Titbh

ITBIT hold time from GCLK rising

Titrsd

InTRANS delay from GCLK rising

Titrsh

InTRANS hold time from GCLK rising

Tltcd

LATECANCEL delay from GCLK falling

Tltch

LATECANCEL hold time from GCLK falling

Tnwh

nWAIT hold time from GCLK rising

Tnws

nWAIT setup time to GCLK falling

Tpasd

PASS output delay from GCLK rising

Tpash

PASS hold time from GCLK rising

Trg0d

RANGEOUT0 output delay

Trg0h

RANGEOUT0 output hold time

Trg1d

RANGEOUT1 output delay

Trg1h

RANGEOUT1 output hold time

Trgen

RANGEOUT0/RANGEOUT1 falling delay from DBGEN falling

Trsth

nRESET hold time from GCLK rising

Trsts

nRESET setup time to GCLK rising

Tsdnd

SDIN output delay from TCK falling

Tsdnh

SDIN hold time from TCK falling

Tshkf

SHCLK1BS/SHCLK2BS falling from TCK changing

Tshkr

SHCLK1BS/SHCLK2BS rising from TCK changing

Ttapidh

TAPID[31:0] hold time to TCK falling

Ttapids

TAPID[31:0] setup time to TCK falling

Ttbe

Delay from TBE rising, to outputs driven valid

Ttbz

Delay from TBE falling, to outputs high impedance

Ttckf

TCK1/TCK2 falling from TCK changing

Ttckh

Minimum TCK HIGH period

Ttckl

Minimum TCK LOW period

Ttckr

TCK1/TCK2 rising from TCK changing

Ttdod

TDO output delay from TCK falling

Ttdoh

TDO hold time from TCK falling

Ttdsd

TDO delay from SDOUTBS changing

Ttdsh

TDO hold time from SDOUTBS changing

Ttekf

TCK falling to ECLK falling delay

Ttekr

TCK rising to ECLK rising delay

Ttoed

nTDOEN output delay from TCK falling

Ttoeh

nTDOEN hold time from TCK falling

Ttpmd

TAPSM[3:0] output delay from TCK falling

Ttpmh

TAPSM[3:0] hold time from TCK falling

Tunis

UNIEN input setup time to GCLK falling

Tunih

UNIEN input hold time to GCLK falling

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