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11.7. MMU test

MMU test allows you to test the following:

  • read and write CAM, RAM1, RAM2, DAC, and lockdown pointer

  • invalidate either a whole TLB or a single entry selected by VA

  • CAM match and RAM1 read.

Table 11.15 shows the MMU test locations. See Chapter 2 Programmer’s Model and Appendix B CP15 Test Registers for more details of the registers used for MMU test.

MMU test locations

Location

Address

Read/write

Burst

Data

Invalidate by VA

0x04

Write

No

31:10

CAM match, RAM1 read

0x08

Write then read

No

31:0

CAM

0x24

Read/write

Yes

31:0

RAM1

0x28

Read/write

Yes

31:0

RAM2

0x2C

Read/write

Yes

31:0

RAM1, RAM2

0x30

Read/write

Yes

31:0

DAC

0x34

Read/write

No

31:0

Lockdown

0x38

Read/write

No

31:20, 1

Invalidate all

0x3C

Write

No

-

The data format for the DAC and lockdown locations are described in Register 3, domain access control register and Register 10, TLB lockdown register.

Invalidate by VA data is organized as shown in Table 11.16.

Invalidate by VA data

Invalidate by VA data

Value

31:10

VA tag

9:0SBZ

Match write data is organized as shown in Table 11.17.

Match write data

Match write data

Value

31:10

VA tag

9:0SBZ

CAM data is organized as shown in Table 11.18.

CAM data

CAM data

Value

31:10

VA tag

9:6

Size_C

(see Table 11.19)

5

Valid

4

Preserved

3:0SBZ

CAM data size encoding is shown in Table 11.19Table 11.19.

CAM data Size_C encoding

Size

Encoding [3:0]

1MB

0b1111

64KB

0b0111

16KB

0b0011

4KB

0b0001

1KB

0b0000

RAM1 data is organized as shown in Table 11.20.

RAM1 data

RAM 1 data

Value

31:25SBZ

24

Protection fault

23

Domain fault

22

MMU miss

21:6

Domain, D15:D0

5

Not cachable

4

Not bufferable

3:0

Access permission

bits [3:0]

For RAM1 reads, bits [24:22] are only valid for a match operation. The encoding of RAM1 data access permission bits is shown in Table 11.21.

RAM1 data access permission bits

Access permission bits [3:0]

Decoded as AP [1:0]

0b0001

0b00

0b0010

0b01

0b0100

0b10

0b1000

0b11

RAM2 data is organized as shown in Table 11.22.

RAM2 data

RAM 2 data

Value

31:10

Physical address TAG

9:6

Size_R2

5:0SBZ

The encoding of RAM2 data size bits is shown in Table 11.23.

RAM2 data Size_R2 encoding

Size_R2

Encoding [3:0]

1MB

0b1111

64KB

0b0111

16KB

0b0011

4KB

0b0000

1KB

0b0001

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