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B.2. Test state register

The test state register is used to modify the behavior of the ARM920T from the default behavior. At reset, all bits of the test state register are cleared to 0.

You can write bits [12:1] by:

MCR	p15,0,Rd,c15,c0,0

You can read bits [12:0] by:

MRC	p15,0,Rd,c15,c0,0

You can only write bit 0 using scan chain 15 (CP15), selecting the test state register. You can also access bits[12:1] using the same scan chain, but it is recommended that you only read and write these using MCR and MRC instructions. The functions of bits in the test state register are listed in Table B.1.

Test state register
BitFunction or nameDescription
12Disable DCache streaming

0 = Enable DCache streaming

1 = Disable DCache streaming

11Disable ICache streaming

0 = Enable ICache streaming

1 = Disable ICache streaming

10Disable DCache linefill

0 = Enable DCache linefills

1 = Disable DCache linefills

9Disable ICache linefill

0 = Enable ICache linefills

1 = Disable ICache linefills

8Disable CP15, c1, bits[31:30]

0 = Enable R1

1 = Disable R1

7iA, StrongARM asynchronous select

00 = FastBus mode

01 = Synchronous mode

10 = Reserved

11 = Asynchronous mode

6nF, StrongARM notFastBus select
5D force noncachable

0 = Normal operation

1 = Force noncachable behavior in the DCache

4I force noncachable

0 = Normal operation

1 = Force noncachable behavior in the ICache

3MMU test

0 = Disable auto-increment

1 = Enable auto-increment

2I miss abort

0 = Enable ITLB hardware page table walks

1 = Disable ITLB hardware page table walks

1D miss abort

0 = Enable DTLB hardware page table walks

1 = Disable DTLB hardware page table walks

0CP15 interpret mode

0 = Disable CP15 interpret mode

1 = Enable CP15 interpret mode

MRC (reading) return bits [12:0], with bits [31:13] being unpredictable.

MCR (writing) update bits [12:1]. Bits [31:13] and [0] should be zero.

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