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B.3. Cache test registers and operations

The ICache and DCache are maintained using MCR and MRC instructions to CP15 registers 7 and 9, defined by the ARM v4T programmer’s model. Additional operations are available using MCR and MRC to CP15 register 15. These operations are combined with those using registers 7 and 9 to enable testing of the caches entirely in software.

A modified subset of these MCR and MRC instructions is available in AMBA test for production test. See Chapter 11 AMBA Test Interface.

All MCR and MRC instructions to CP15 are available through the debug scan chains in CP15 interpret mode. This mode of access is intended to be used with a subset of the available CP15 MCR and MRC instructions, such that using other than the minimal subset will cause unpredictable behavior. See Chapter 9 Debug Support.

The register 7 operations are all write-only. They are listed in Table B.3.

Register 7 operations
CacheFunction
I and D, or I, or DInvalidate cache
I or DInvalidate single entry using MVA
DClean single entry using MVA or index
DClean and invalidate single entry using MVA or index
IPrefetch cache line using MVA

The register 9 operations are read and write. They are listed in Table B.4.

Register 9 operations
CacheFunction
I or DRead lockdown base (applies to all cache segments).
I or DWrite victim and lockdown base (applies to all cache segments).
I or DWrite victim for specified segment. This is provided for debug only and is not specified by ARMv4T.

The register 15 operations are listed in Table B.5.

Register 15 operations
CacheFunctionRdData
I and D, or I, or DSet dirty all entriesSBZ-
I and D, or I, or DCAM read to C15.C.<I or D>SegTag, Dirty, Index
I and D, or I, or DCAM writeTag, Seg, Dirty-
I and D, or I, or DRAM read to C15.C.<I or D>Seg, WordData
I and D, or I, or DRAM write from C15.C.<I or D>Seg, Word-
I and D, or I, or DCAM match RAM read to reg C15.C.<I or D>Tag, Seg, WordHit or Miss, Data

The Harvard architecture allows you to combine all of these operations to operate on both the ICache and DCache in parallel.

Note

For the CAM Match, RAM Read operation the respective MMU does not perform a lookup and a cache miss does not cause a linefill.

These register 15 operations are all issued as MCR. In these, Rd defines the address for the operation. Therefore, the data is either supplied from, or latched into, the CP15.C.I or CP15.C.D in CP15. These 32 bit registers are accessed with the CP15 MCR and MRC instructions shown in Table B.6.

CP15 MCR and MRC instructions
CacheFunction
I and D, or I, or DWrite to register CP15.C.<I or D>
I or DRead from register CP15.C.<I or D>

Again, the Harvard architecture allows the data to be written to both CP15.C.<I and D> in parallel.

Table B.7 summarizes C7, C9, and C15 operations.

Register 7, 9, and 15 operations

Function

Rd

Instruction

 

Invalidate ICache and DCache

SBZ

MCR p15,0,Rd,c7,c7,0

Invalidate ICache

SBZ

MCR p15,0,Rd,c7,c5,0

Invalidate ICache single entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c5,1

Prefetch ICache line (using MVA)

MVA format

MCR p15,0,Rd,c7,c13,1

Invalidate DCache

SBZ

MCR p15,0,Rd,c7,c6,0

Invalidate DCache single entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c6,1

Clean DCache single entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c10,1

Clean and invalidate DCache entry (using MVA)

MVA format

MCR p15,0,Rd,c7,c14,1

Clean DCache single entry (using index)

Index format

MCR p15,0,Rd,c7,c10,2

Clean and invalidate DCache entry (using index)

Index format

MCR p15,0,Rd,c7,c14,2

Drain write buffer [1]

SBZ

MCR p15,0,Rd,c7,c10,4

Wait for interrupt [2]

SBZ

MCR p15,0,Rd,c7,c0,4

 

Read DCache lockdown base

Base

MRC p15,0,Rd,c9,c0,0

Write DCache victim and lockdown base

Victim=Base

MCR p15,0,Rd,c9,c0,0

Write DCache victimVictim, SegMCR p15,0,Rd,c9,c1,0

Read ICache lockdown base

Base

MRC p15,0,Rd,c9,c0,1

Write ICache victim and lockdown base

Victim=Base

MCR p15,0,Rd,c9,c0,1

Write ICache victimVictim, SegMCR p15,0,Rd,c9,c1,1
 

I set dirty all entries

SBZ

MCR p15,2,Rd,c15,c1,0

D set dirty all entries

SBZ

MCR p15,2,Rd,c15,c2,0

I and D set dirty all entries

SBZ

MCR p15,2,Rd,c15,c3,0

 

I CAM read to C15.C.I

Seg

MCR p15,2,Rd,cI5,c5,2

D CAM read to C15.C.D

Seg

MCR p15,2,Rd,c15,c6,2

I CAM read to C15.C.I and

D CAM read to C15.C.D

Seg

MCR p15,2,Rd,c15,c7,2

 

I CAM write

Tag, Seg, Dirty

MCR p15,2,Rd,c15,c5,6

D CAM write

Tag, Seg, Dirty

MCR p15,2,Rd,c15,c6,6

I and D CAM write

Tag, Seg, Dirty

MCR p15,2,Rd,c15,c7,6

 

I RAM read to C15.C.I

Seg, Word

MCR p15,2,Rd,c15,c9,2

D RAM read to C15.C.D

Seg, Word

MCR p15,2,Rd,c15,c10,2

I RAM read to C15.C.I and

D RAM read to C15.C.D

Seg, Word

MCR p15,2,Rd,c15,c11,2

 

I RAM write from C15.C.I

Seg, Word

MCR p15,2,Rd,c15,c9,6

D RAM write from C15.C.D

Seg, Word

MCR p15,2,Rd,c15,c10,6

I RAM write from C15.C.I and

D RAM write from C15.C.D

Seg, Word

MCR p15,2,Rd,c15,c11,6

 

I CAM match, RAM read to C15.C.I

Tag, Seg, Word

MCR p15,2,Rd,c15,c5,5

D CAM match, RAM read to C15.C.D

Tag, Seg, Word

MCR p15,2,Rd,c15,c6,5

I CAM match, RAM read to C15.C.I and

D CAM match, RAM read to C15.C.D

Tag, Seg, Word

MCR p15,2,Rd,c15,c7,5

 

Write to C15.C.I

Data

MCR p15,3,Rd,c15,c1,0

Write to C15.C.D

Data

MCR p15,3,Rd,c15,c2,0

Write to C15.C.I and

write to C15.C.D

Data

MCR p15,3,Rd,c15,c3,0

Read from C15.C.I

Data read

MRC p15,3,Rd,c15,c1,0

Read from C15.C.D

Data read

MRC p15,3,Rd,c15,c2,0

[1] Stops execution until the write buffer has drained.

[2] Stops execution in a LOW power state until an interrupt occurs.

The CAM read format for Rd is shown in Figure B.2.

Figure B.2. Rd format, CAM read

Figure B.2. Rd format, CAM read

The CAM write format for Rd is shown in Figure B.3.

Figure B.3. Rd format, CAM write

Figure B.3. Rd format, CAM write

In Figure B.3, bit labels have the following meanings:

V

Valid

De

Dirty even (words [3:0])

Do

Dirty odd (words [7:4])

WB

Writeback.

The RAM read format for Rd is shown in Figure B.4.

Figure B.4. Rd format, RAM read

Figure B.4. Rd format, RAM read

The RAM write format for Rd is shown in Figure B.5.

Figure B.5. Rd format, RAM write

Figure B.5. Rd format, RAM write

The CAM match, RAM read format for Rd is shown in Figure B.6.

Figure B.6. Rd format, CAM match RAM read

Figure B.6. Rd format, CAM match RAM read

The CAM read format for data is shown in Figure B.7.

Figure B.7. Data format, CAM read

Figure B.7. Data format, CAM read

In AMBA cache test mode, the LFSR for the cache is restricted to increment only on a CAM read.

The RAM read format for data is shown in Figure B.8.

Figure B.8. Data format, RAM read

Figure B.8. Data format, RAM read

The CAM match, RAM read format for data is shown in Figure B.9.

Figure B.9. Data format, CAM match RAM read

Figure B.9. Data format, CAM match RAM read
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