The ITLB and DTLB are maintained using
to CP15 registers 2, 3, 5, 6, 8, and 10, defined by the ARM v4T
programmer’s model. Additional operations are available using
to CP15 register 15. These operations are combined with those using
registers 2, 3, 5, 6, 8, and 10 to enable testing of the TLBs entirely
A modified subset of these
are available in AMBA test for production test. See Chapter 11 AMBA Test Interface.
to CP15 are available through the debug scan chains in CP15 Interpret
Mode. This mode of access is intended to be used with a subset of
the available CP15
so that using other than the minimal subset causes unpredictable
behavior. See Scan chains 4 and 15, the ARM920T
The register 2 operations are read and write. They are extended by the register 15 operations to allow individual control of the separate I and D Translation Table Base (TTB) registers, and are listed in Table B.9.
|c2||I and D||Write I and D TTB registers|
|c2||D||Read D TTB register|
|c15||I||Write I TTB register|
|c15||D||Write D TTB register|
|c15||I||Read I TTB register|
The register 3 operations are read and write. They are extended by the register 15 operations to allow individual control of the separate I and D Domain Access Control (DAC) registers, and are listed in Table B.10.
|c3||I and D||Write I and D DAC registers|
|c3||D||Read D DAC register|
|c15||I||Write I DAC register|
|c15||D||Write D DAC register|
|c15||I||Read I DAC register|
The register 5 operations are read and write, but the ability to access the I FSR is not architecturally defined in ARMv4T and is only intended for debug, when testing the TLB miss mechanism using aborts rather than hardware page table walks. Register 5 operations are listed in Table B.11. The register 15 duplication remains from ARM920T Rev 0.
|c5||I or D||Write Fault Status Register (FSR)|
|c5||I or D||Read FSR|
|c15||I||Write I FSR|
|c15||I||Read I FSR|
The register 6 operations are read and write. The I TLB is
identical to the D TLB, but the I FAR is not architecturally defined,
so the ability to access the I FAR is for testability only and the
are described by the ARMv4T as being UNPREDICTABLE. Register 6 operations
are listed in Table B.12.
The register 8 operations are all write-only. They are listed in Table B.13.
|c8||I and D, or I, or D||Invalidate TLB|
|c8||I or D||Invalidate single entry using MVA|
The register 10 operations are read and write. They are listed in Table B.14.
|c10||I or D||Read victim, lockdown base and preserve bit|
|c10||I or D||Write victim, lockdown base and preserve bit|
The register 15 operations that operate on the CAM, RAM1, and RAM2 are listed in Table B.15.
|I or D||CAM read to C15.M.<I or D>||SBZ||Tag, Size, V, P|
|I and D, or I, or D||CAM write||Tag, Size, V, P|
|I or D||RAM1 read to C15.M.<I or D>||SBZ||Protection|
|I and D, or I, or D||RAM1 write||Protection|
|I or D||RAM2 read to C15.M.<I or D>||SBZ||PA Tag, Size|
|I and D, or I, or D||RAM2 write||PA Tag, Size||PA Tag, Size|
|I or D||CAM match RAM1 read to C15.M.<I or D>||MVA||Fault, Miss, Protection|
While the ARM920T memory system is a Harvard architecture, the TLBs are accessed using CData. This means the write operations can be combined to operate on both the I TLB and D TLB in parallel.
Setting the CP15 register 15 test status register MMU test bit (bit 3) enables auto-increment of the TLB index pointer in both MMUs on CAM and RAM1 reads and writes. If this bit is not set, the TLB index pointer only increments on RAM1 writes.
For the CAM match, RAM1 read operation a TLB miss does not cause a page walk.
These register 15 operations are all issued as
which means that the read and match operations have to be latched
into the CP15.M.I or CP15.M.D in CP15. These are 32 bit registers
that are read with the following CP15
Read from register CP15.M.<I or D>
Table B.16 summarizes C2, C3, C5, C6, C8, C10, and C15 operations.
|Read TTB register||TTB|
|Write TTB register||TTB|
|Read domain 15:0 access control||DAC|
|Write domain 15:0 access control||DAC|
|Read data FSR value||FSR|
|Write data FSR value||FSR|
|Read prefetch FSR value ||FSR|
|Write prefetch FSR value a||FSR|
|Read D FAR||FAR|
|Write D FAR||FAR|
|Read I FAR a||FAR|
|Write I FAR a||FAR|
Invalidate I TLB
Invalidate I TLB single entry (using MVA)
Invalidate D TLB
Invalidate D TLB single entry (using MVA)
Read D TLB lockdown
Write D TLB lockdown
Read I TLB lockdown
Write I TLB lockdown
Read I TTB
Write I TTB
Write D TTB
Read I DAC
Write I DAC
Write D DAC
|Read prefetch FSR value||FSR|
|Write prefetch FSR value||FSR|
D CAM read to C15.M.D
I CAM read to C15.M.I
D CAM write
|Tag, Size, V, P|
I CAM write
Tag, Size, V, P
D and I CAM write
Tag, Size, V, P
D RAM1 read to C15.M.D
I RAM 1 read to C15.M.I
D RAM1 write
I RAM 1 write
D and I RAM1 write
D RAM2 read to C15.M.D
I RAM2 read to C15.M.I
D RAM2 write
PA Tag, Size
I RAM2 write
PA Tag, Size
D and I RAM2 write
PA Tag, Size
D CAM match, RAM1 read to C15.M.D
I CAM match, RAM1 read to C15.M.I
 These MCR and MRC instructions are not architecturally defined in ARMv4T, and are only intended for testability. Their behavior is described by ARMv4T as being UNPREDICTABLE.
Figure B.12 shows the format of Rd for CAM writes and data for CAM reads.
Figure B.13 shows the format of Rd for RAM1 writes.
Figure B.14 shows the data format for RAM1 reads.
|Prot fault||Domain fault||TLB miss||Function|
|0||1||0||Hit, domain fault|
|1||0||0||Hit, protection fault|
|1||1||0||Hit, protection and domain fault|
Figure B.15 shows the Rd format for RAM2 writes, and the data format for RAM2 reads.
|SIZE_R2[3:0]||Memory region size|
The encoding for SIZE_R2 is different from SIZE_C.