You copied the Doc URL to your clipboard.

B.5. StrongARM backwards compatibility operations

The following MCR instructions are supported to provide clock switching and MCR wait for interrupt compatibility with SA110 and SA1100 (StrongARM).

MCR	p15,0,Rd,c15,c1,2			; Enable clock switching

This is equivalent to Asynchronous clocking mode.

MCR	p15,0,Rd,c15,c2,2			; Disable clock switching 

This is equivalent to FastBus clocking mode.

MCR	p15,0,Rd,c15,c8,2			; Wait for interrupt

This is equivalent to MCR p15,0,Rd,c7,c0,4.

These three MCR instructions must not be used and are deprecated in ARM architectures after v4T.

Was this page helpful? Yes No