The ARM920T processor has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK. This can be seen on the CPCLK output as shown in Figure Clock Modes.1. GCLK can be sourced from either BCLK or FCLK depending on the clocking mode, selected using nF bit and iA bit in CP15 register 1 (see Register 1, control register on page 2-12), and external memory access. The three clocking modes are:
The ARM920T is a static design and you can stop both clocks indefinitely without loss of state. Figure Clock Modes.1 shows that some of the ARM920T macrocell signals have timing specified with relation to GCLK. This can be either FCLK or BCLK depending on the clocking mode.