You copied the Doc URL to your clipboard.

Clock Modes.3. Synchronous mode

In this mode of operation GCLK is sourced from BCLK or FCLK. There are three restrictions that apply to BCLK and FCLK:

  • FCLK must have a higher frequency than BCLK

  • FCLK must be an integer multiple of the BCLK frequency

  • FCLK must be HIGH whenever there is a BCLK transition.

BCLK is used to control the AMBA ASB interface, and FCLK is used to control the internal ARM920T processor core. When an external memory access is required the core either continues to clock using FCLK or is switched to BCLK, as shown in Table Clock Modes.1. This is the same as for asynchronous mode.

Clock selection for external memory accesses
External memory access operationGCLK =
Buffered writeFCLK
Nonbuffered writeBCLK
Page walk, cachable read (linefill), noncachable readBCLK

The penalty in switching from FCLK to BCLK and from BCLK to FCLK is symmetric, from zero to one phase of the clock to which the core is re-synchronizing. That is, switching from FCLK to BCLK has a penalty of between zero and one BCLK phase, and switching back from BCLK to FCLK has a penalty of between zero and one FCLK phase.

Figure Clock Modes.2 shows an example zero BCLK phase delay when switching from FCLK to BCLK in synchronous mode.

Figure Clock Modes.2. Synchronous mode FCLK to BCLK zero phase delay

Figure Clock Modes.2. Synchronous mode
FCLK to BCLK zero phase delay

Figure Clock Modes.3 shows an example one BCLK phase delay when switching from FCLK to BCLK in synchronous mode.

Figure Clock Modes.3. Synchronous mode FCLK to BCLK one phase delay

Figure Clock Modes.3. Synchronous mode FCLK to BCLK one
phase delay
Was this page helpful? Yes No