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Clock Modes.4. Asynchronous mode

In this mode of operation GCLK is sourced from BCLK or FCLK. FCLK and BCLK can be completely asynchronous to one another, with the one restriction that FCLK must have a higher frequency than BCLK.

BCLK is used to control the AMBA ASB interface, and FCLK is used to control the internal ARM920T processor core. When an external memory access is required the core either continues to clock using FCLK or is switched to BCLK. This is the same as for synchronous mode.The penalty in switching from FCLK to BCLK and from BCLK to FCLK is symmetric, from zero to one cycle of the clock to which the core is re-synchronizing. That is, switching from FCLK to BCLK has a penalty of between zero and one BCLK cycle, and switching back from BCLK to FCLK has a penalty of between zero and one FCLK cycle.

Figure Clock Modes.4 shows an example zero BCLK cycle delay when switching from FCLK to BCLK in asynchronous mode.

Figure Clock Modes.4. Asynchronous mode FCLK to BCLK zero cycle delay

Figure Clock Modes.4. Asynchronous mode
FCLK to BCLK zero cycle delay

Figure Clock Modes.5 shows an example one BCLK cycle delay when switching from FCLK to BCLK in asynchronous mode.

Figure Clock Modes.5. Asynchronous mode FCLK to BCLK one cycle delay

Figure Clock Modes.5. Asynchronous mode FCLK to BCLK one
cycle delay
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