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7.7. Busy-waiting and interrupts

The coprocessor is permitted to stall (or busy-wait) the processor during the execution of a coprocessor instruction if, for example, it is still busy with an earlier coprocessor instruction. To do so, the coprocessor associated with the Decode stage instruction must drive WAIT in CHSDE[1:0]. When the instruction concerned enters the Execute stage of the pipeline, the coprocessor can drive WAIT onto CHSEX[1:0] for as many cycles as required to keep the instruction in the busy-wait loop.

For interrupt latency reasons the coprocessor can be interrupted while busy-waiting, causing the instruction to be abandoned. Abandoning execution is achieved through CPPASS. The coprocessor must monitor the state of CPPASS during every busy-wait cycle. If it is HIGH, the instruction must still be executed. If it is LOW, the instruction must be abandoned. Figure 7.7 shows a busy-waited coprocessor instruction being abandoned due to an interrupt.

Figure 7.7. ARM920T busy waiting and interrupts

Figure 7.7. ARM920T busy waiting and interrupts
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