This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.
A mechanism that indicates to a core that it should halt execution of an attempted illegal memory access. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. An abort is classified as either a prefetch abort, a data abort, or an external abort. See also Data abort, External abort and Prefetch abort.
- Abort model
An abort model is the defined behavior of an ARM processor in response to a Data Abort exception. Different abort models behave differently with regard to load and store instructions that specify base register writeback.
See Arithmetic Logic Unit.
- Application Specific Integrated Circuit
An integrated circuit that has been designed to perform a specific application function. It can be custom-built or mass-produced.
- Arithmetic Logic Unit
The part of a processor core that performs arithmetic and logic operations.
- ARM state
A processor that is executing ARM (32-bit) word-aligned instructions is operating in ARM state.
See Application Specific Integrated Circuit.
- Banked registers
Those physical registers whose use is defined by the current processor mode. The banked registers are R8 to R14.
- Base register
A register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation.
Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory. See also Little-endian and Endianness.
A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to allow inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested. See also Watchpoint.
An 8-bit data item.
A block of on-chip or off-chip fast access memory locations, situated between the processor and main memory, used for storing and retreiving copies of often used instructions and/or data. This is done to greatly reduce the average speed of memory accesses and so to increase processor performance.
- Cache contention
When the number of frequently-used memory cache lines that use a particular cache set exceeds the set-associativity of the cache. In this case, main memory activity increases and performance decreases.
- Cache hit
A memory access that can be processed at high speed because the instruction or data that it addresses is already held in the cache.
- Cache line index
The number associated with each cache line in a cache set. Within each cache set, the cache lines are numbered from 0 to (set associativity) -1.
- Cache lockdown
To fix a line in cache memory so that it cannot be overwritten. Cache lockdown allows critical instructions and/or data to be loaded into the cache so that the cache lines containing them will not subsequently be reallocated. This ensures that all subsequent accesses to the instructions/data concerned are cache hits, and therefore complete as quickly as possible.
- Cache miss
A memory access that cannot be processed at high speed because the instruction/data it addresses is not in the cache and a main memory access is required.
See Content addressable memory.
- Central Processing Unit
The part of a processor that contains the ALU, the registers, and the instruction decode logic and control circuitry. Also commonly known as the processor core.
- Clock gating
Gating a clock signal for a macrocell with a control signal (such as PWRDOWN) and using the modified clock that results to control the operating state of the macrocell.
- Condition field
A 4-bit field in an instruction that is used to specify a codition under which the instruction can execute.
- Content addressable memory
Memory that is identified by its contents. Content addressable memory is used in CAM-RAM architecture caches to store the tags for cache entries.
A processor that supplements the main CPU. It carries out additional functions that the main CPU cannot perform. Usually used for floating-point math calculations, signal processing, or memory management.
See Central Processing Unit.
- Data Abort
An indication from a memory system to a core that it should halt execution of an attempted illegal memory access. A data abort is attempting to access invalid data memory. See also Abort, External abort and Prefetch abort.
- Data cache
A block of on-chip fast access memory locations, situated between the processor and main memory, used for storing and retreiving copies of often used data. This is done to greatly reduce the average speed of memory accesses and so to increase processor performance.
A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.
A collection of sections, large pages and small pages of memory, which can have their access permissions switched rapidly by writing to the Domain Access Control Register (CP15 register 3).
- Double word
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
The additional JTAG-based hardware provided by debuggable ARM processors to aid debugging.
Byte ordering. The scheme that determines the order in which successive bytes of a data word are stored in memory. See also Little-endian and Big-endian.
- Exception vector
One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt service routine.
- External abort
An indication from an external memory system to a core that it should halt execution of an attempted illegal memory access. An external abort is caused by the external memory system as a result of attempting to access invalid memory. See also Abort, Data abort and Prefetch abort.
A 16-bit data item.
A block of on-chip fast access memory locations, situated between the processor and main memory, used for storing and retreiving copies of often used instructions. This is done to greatly reduce the average speed of memory accesses and so to increase processor performance.
- Instruction cache
- Joint Test Action Group
The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.
See Joint Test Action Group.
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also Big-endian and Endianness.
A complex logic block with a defined interface and behavior. A typical VLSI system will comprise several macrocells (such as an ARM9E-S, an ETM9, and a memory block) plus application-specific logic.
- Prefetch abort
An indication from a memory system to a core that it should halt execution of an attempted illegal memory access. A prefetch abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory. See also Data abort, External abort and Abort.
A contraction of microprocessor. A processor includes the CPU or core, plus additional components such as memory, and interfaces. These are combined as a single macrocell, that can be fabricated on an integrated circuit.
A partition of instruction or data memory space.
A temporary storage location used to hold binary data until it is ready to be used.
See Should be one.
See Should be zero.
The currently selected scan chain number in an ARM TAP controller.
- Should be one
Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 will produce UNPREDICTABLE results.
- Should be zero
Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 will produce UNPREDICTABLE results.
- Tag bits
The index or key field of a CAM entry.
See Test access port.
- Test Access Port
The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST.
- Thumb state
A processor that is executing Thumb (16-bit) half-word aligned instructions is operating in Thumb state.
An instruction that generates an undefined instruction exception.
For reads, the data returned when reading from this location is unpredictable. It can have any value. For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration. UNPREDICTABLE instructions must not halt or hang the processor, or any part of the system.
A watchpoint is a mechanism provided by debuggers to halt program execution when the data contained by a particular memory address is changed. Watchpoints are inserted by the programmer to allow inspection of register contents, memory locations, and variable values when memory is written to test that the program is operating correctly. Watchpoints are removed after the program is successfully tested. See also Breakpoint.
A 32-bit data item.