The ARM920T processor is a member of the ARM9TDMI family of general-purpose microprocessors, which includes:
ARM940T (core plus cache and protection unit)
ARM920T (core plus cache and MMU).
The ARM9TDMI processor core is a Harvard architecture device implemented using a five-stage pipeline consisting of Fetch, Decode, Execute, Memory, and Write stages. It can be provided as a standalone core that can be embedded into more complex devices. The standalone core has a simple bus interface that allows you to design your own caches and memory systems around it.
The ARM9TDMI family of microprocessors supports both the 32-bit ARM and 16-bit Thumb instruction sets, allowing you to trade off between high performance and high code density.
The ARM920T processor is a Harvard cache architecture processor that is targeted at multiprogrammer applications where full memory management, high performance, and low power are all-important. The separate instruction and data caches in this design are 16KB each in size, with an 8-word line length. The ARM920T processor implements an enhanced ARM architecture v4 MMU to provide translation and access permission checks for instruction and data addresses.
The ARM920T processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM920T processor also includes support for coprocessors, exporting the instruction and data buses along with simple handshaking signals.
The ARM920T interface to the rest of the system is over unified address and data buses. This interface enables implementation of either an Advanced Microcontroller Bus Architecture (AMBA) Advanced System Bus (ASB) or Advanced High-performance Bus (AHB) bus scheme either as a fully-compliant AMBA bus master, or as a slave for production test. The ARM920T processor also has a Tracking ICE mode which allows an approach similar to a conventional ICE mode of operation.
The ARM920T processor supports the addition of an Embedded Trace Macrocell (ETM) for real-time tracing of instructions and data.