The ARM920T processor incorporates the ARM9TDMI integer core, which implements the ARM architecture v4T. It executes the ARM and Thumb instruction sets, and includes EmbeddedICE JTAG software debug features.
The programmer’s model of the ARM920T processor consists of the programmer’s model of the ARM9TDMI core (see About the ARM9TDMI programmer’s model) with the following additions and modifications:
The ARM920T processor incorporates two coprocessors:
CP14, which allows software access to the debug communications channel. You can access the registers defined in CP14 using
MRCinstructions. These are described in Debug communications channel.
The system control coprocessor, CP15, which provides additional registers that are used to configure and control the caches, MMU, protection system, the clocking mode, and other system options of the ARM920T, such as big or little-endian operation. You can access the registers defined in CP15 using
MRCinstructions. These are described in CP15 register map summary.
The ARM920T processor also features an external coprocessor interface that allows the attachment of a closely-coupled coprocessor on the same chip, for example, a floating-point unit. You can access registers and operations provided by any coprocessors attached to the external coprocessor interface using appropriate coprocessor instructions.
Memory accesses for instruction fetches and data loads and stores can be cached or buffered. Cache and write buffer configuration and operation is described in detail in Chapter 4 Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM.
The MMU page tables that reside in main memory describe the virtual to physical address mapping, access permissions, and cache and write buffer configuration. These are created by the operating system software and accessed automatically by the ARM920T MMU hardware whenever an access causes a TLB miss.
The ARM920T has a Trace Interface Port that allows the use of Trace hardware and tools for real-time tracing of instructions and data.