All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM TAP controller, and is assigned scan chain 6.
The scan chain consists of a 40-bit shift register comprising:
a 32-bit data field
a 7-bit address field
a read/write bit.
The general arrangement of the ETM9 JTAG registers is shown in Figure 2.1.
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored.
A read or a write takes place when the TAP controller enters the UPDATE-DR state.
For further details of ETM9 registers, see the Embedded Trace Macrocell Specification.