EtmMuxDemux module takes the standard
trace port interface from the ETM9 and, using the CLK, PWRDOWN, ETMnRESET, PORTMODE, and CLKDIVTWOEN outputs, converts the trace
to the correct port mode. The example HDL for configuring the trace
port is not part of the ETM9 macrocell HDL. It is provided in an
ETM9/EtmMuxDemux.v in the ETM9
Refer to Clocks and resets for more information on CLK and nRESET.
When instantiating your
EtmMuxDemuxmodule, ensure that you wire all 16 TRACEPKT signals to all 16 TRACEPKTetm[15:0] signals.
Ensure that the
EtmMuxDemuxCLK input is wired to the ETM CLK and not the core clock.
EtmMuxDemuxnRESET is wired to the ETM nRESET and not the core reset.