The GPIOPCellID0-3 registers are four 8-bit wide registers,
that span address locations 0xFF0-0xFFC.
The registers can conceptually be treated as a 32-bit register.
The register is used as a standard cross-peripheral identification
system. The GPIOPCellID register is set to 0xB105F00D. Figure 3.2 shows the bit
assignment for the GPIOPCellID0-3 registers.
The four 8-bit PrimeCell identification registers are described in the following subsections:
The GPIOPCellID0 register is hard coded and the fields within the register determine the reset value. Table 3.16 shows the bit assignment of the GPIOPCellID0 register.
The GPIOPCellID1 register is hard coded and the fields within the register determine the reset value. Table 3.17 shows the bit assignment of the GPIOPCellID1 register.
The GPIOPCellID2 register is hard coded and the fields within the register determine the reset value. Table 3.18 shows the bit assignment of the GPIOPCellID2 register.
The GPIOPCellID3 register is hard coded and the fields within the register determine the reset value. Table 3.19 shows the bit assignment of the GPIOPCellID3 register.