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2.3.5. Mode control

You can control the PrimeCell GPIO lines through the hardware control interface. The mode of each line is selected by the mode control register. When hardware control is enabled in a particular line, the data and data direction control signals of the corresponding PrimeCell GPIO pins are ignored. Data and control transfers over these PrimeCell GPIO pins are then driven or read by some external auxiliary control block.

See Figure 2.6 for a block diagram showing the mode control multiplexor.

Figure 2.6. Mode control multiplexor

Figure 2.6. Mode control multiplexor

Table 2.2 shows how the pads are configured for hardware and software control.

Pad configuration
 HardwareSoftware
OutputInputOutputInput

7

6

5

4

3

2

1

0

Mode control register, GPIOAFSEL11

1

10000
Hardware enable input, nGPAFEN0011

x

x

x

x

Hardware data input, GPAFOUTABxxxxxx
Hardware data output, GPAFINABcd0000
Software enable output, GPIODIRxxxx1100
Software data output, GPIODATAxxxxEFgh
Software data input, GPINABcdEFgh
Pad enable, nGPEN00110011
Pad output, GPOUTABxxEFxx
Pad input, GPINABcdEFgh
Bidirectional pad, XPABcdEFgh

Note

A, B, E, F, are sources of output data. c, d, g, h, are sources of input data.

In hardware control mode the GPIODATA register can also read the values of lines configured as inputs.

Table 2.2 is a concise truth table of operation when the GPIO PL061 has its data port pins configured as both software and hardware controlled. The values that exist on the bidirectional XP[7:0] lines are shown as the last row within the table, but it is realized that they have different sources as described below.

Table 2.2 is best explained by considering each mode separately.

Hardware control mode

The left hand four columns of Table 2-2 relate to the hardware mode of operation.XP[7:4] pins have been configured as being under hardware control by setting the respective bits to 1 within the GPIOAFSEL register.Pins configured as outputs:

  • XP[7:6] pins are configured as outputs by applying a 0 value to the respective nGPAFEN port signals.

  • XP[7:6] data values are sourced from the GPAFOUT[7:6] port input signals, shown as (A,B). These values are propagated and driven out onto the XP[7:6] pins. These values are also transferred back to the GPAFIN[7:6] port output signals through the GPIN[7:6] pins. This feature also allows the XP[7:0] values to be read through the APB interface GPIODATA register.

Pins configured as inputs:

  • XP[5:4] pins are configured as inputs by applying a 1 value to the respective nGPAFEN port signals.

  • XP[5:4] values are driven from an external source, and as above, these values (c, d), are transferred to GPAFIN[5:4] signals. Again, the XP[7:0] can be read through the APB interface GPIODATA register.

Software control

The right hand four columns of Table 2-2 relate to the software mode of operation. In software mode the GPAFIN port signals are forced LOW as a power saving feature.XP[3:0] pins have been configured as being under software control by setting the respective bits to 0 within the GPIOAFSEL register.Pins configured as outputs:

  • XP[3:2] pins are configured as outputs by setting the respective bits to 1 within the GPIODIR data direction register.

  • XP[3:2] data values are sourced from the GPIODATA[3:2] register bits, shown as (E,F). These values are propagated and driven out onto the XP[3:2] pins. These values are transferred back to the GPIN[3:2] pins, but not to the GPAFIN pins as this route is disabled when in software mode.

  • The XP[3:2] pin values can be read through the APB interface GPIODATA register.

Pins configured as inputs:

  • XP[1:0] pins have been configured as inputs by setting the respective bits to 0 within the GPIODIR data direction register.

  • XP[1:0] values are driven from an external source, shown as (g, h). The XP[1:0] pin values can be read through the APB interface GPIODATA register.

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