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3.3.6. Interrupt mask register, GPIOIE

The GPIOIE register is the interrupt mask register. Bits set to HIGH in GPIOIE allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset.

Table 3.7 shows the bit assignment of the GPIOIE register.

GPIOIE register

Bits

Name

Type

Function

7:0

Interrupt mask register

Read/write

Bits set, corresponding pin is not masked.

Bits cleared, corresponding pin interrupt is masked.

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