You copied the Doc URL to your clipboard.

3.3.11. Peripheral identification registers, GPIOPeriphID0-3

The GPIOPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a 32-bit register. The read only registers provide the following options of the peripheral:

PartNumber[11:0]

This is used to identify the peripheral. The three digits product code 0x061 is used.

Designer ID[19:12]

This is the identification of the designer. ARM Ltd is 0x41 (ASCII A).

Revision[23:20]

This is the revision number of the peripheral. The revision number starts from 0.

Configuration[31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.1 shows the bit assignment for the GPIOPeriphID0-3 registers.

Figure 3.1. Peripheral identification register bit assignment

Figure 3.1. Peripheral identification register
bit assignment

Note

When you design a systems memory map you must remember that the PrimeCell GPIO has a 4KB memory footprint. All memory accesses to the peripheral identification registers must be 32-bit, using the LDR and STR instructions.

The four, 8-bit peripheral identification registers are described in the following subsections:

GPIOPeriphID0 register

The GPIOPeriphID0 register is hard coded and the fields within the register determine the reset value. Table 3.12 shows the bit assignment of the GPIOPeriphID0 register.

GPIOPeriphID0 register
Bits Name

Description

15:8

-

Reserved, read undefined must read as zeros

7:0

PartNumber0

These bits read back as 0x61

GPIOPeriphID1 register

The GPIOPeriphID1 register is hard coded and the fields within the register determine the reset value. Table 3.13 shows the bit assignment of the GPIOPeriphID1 register.

GPIOPeriphID1 register
Bits Name

Description

15:8

-

Reserved, read undefined, must read as zeros

7:4

Designer0

These bits read back as 0x1

3:0

PartNumber1

These bits read back as 0x0

GPIOPeriphID2 register

The GPIOPeriphID2 register is hard coded and the fields within the register determine the reset value. Table 3.14 shows the bit assignment of the GPIOPeriphID2 register.

GPIOPeriphID2 register
Bits Name

Description

15:8

-

Reserved, read undefined, must read as zeros

7:4

Revision

These bits read back as 0x0

3:0

Designer1

These bits read back as 0x4

GPIOPeriphID3 register

The GPIOPeriphID3 register is hard coded and the fields within the register determine the reset value. Table 3.15 shows the bit assignment of the GPIOPeriphID3 register.

GPIOPeriphID3 register
Bits Name

Description

15:8

-

Reserved, read undefined, must read as zeros

7:0

Configuration

These bits read back as 0x00

Was this page helpful? Yes No