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6.1. About the BIU and write buffer

The ARM946E-S processor supports the Advanced Microprocessor Bus Architecture (AMBA) Advanced High-performance Bus (AHB) interface. The AHB is a new generation of AMBA interface that addresses the requirements of high-performance synthesizable designs, including:

  • single clock edge operation (rising edge)

  • unidirectional (nontristate) buses

  • burst transfers

  • split transactions

  • single-cycle bus master handover.

See the AMBA Rev 2.0 AHB Specification for full details of this bus architecture.

The ARM946E-S BIU implements a fully-compliant AHB bus master interface and incorporates a write buffer to increase system performance. The BIU is the link between the ARM9E-S core with the caches and Tightly-Coupled Memory (TCM) and the external AHB memory. The AHB memory must be accessed for cache linefills and for initializing the TCMs, and to access code and data that are not within the cachable or TCM address regions.

When an AHB access is performed, the BIU and system controller handshake to ensure that the ARM9E-S core is stalled until the access has been performed. If you are using the write buffer, you might be able to enable the core to continue program execution. The BIU controls the write buffer and related stall behavior.