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6.5. The write buffer

The ARM946E-S processor provides a write buffer to improve system performance. The write buffer has a 16-entry FIFO. Each entry can be either address or data. The type of entry is determined by the setting of an address/data flag. Each address entry is tagged with the size of transfer, as indicated by the ARM9E-S core (byte, halfword, or word).

Write buffer behavior is controlled by the protection region attributes of the store being performed and the data cache and protection unit enable status. This control is represented by the data Cachable bit (Cd) and the write Buffer control bit (Bd) from the protection unit. These control bits are generated as follows:

Cd bit

This is generated from the cachable attribute of the protection region AND the data cache enable AND the protection unit enable.

Bd bit

This is generated from the bufferable attribute for the protection region AND the protection unit enable.

All accesses are initially noncachable and nonbufferable until you have programmed and enabled the protection unit. Therefore, you cannot use the write buffer while the protection unit is disabled.

On reset, all entries in the write buffer are invalidated.