You copied the Doc URL to your clipboard.

5.5.3. Stall cycles for Instruction TCM accesses

Simultaneous instruction fetch and data reads of the Instruction TCM incur a single stall cycle. This is because the Instruction TCM is a single port memory, which can only return a single word of memory per clock cycle. This is shown in Figure 5.3.

Figure 5.3. Simultaneous instruction fetch and data read of Instruction TCM

Figure 5.3. Simultaneous instruction fetch and
data read of Instruction TCM

A data write to the Instruction TCM followed by a data read from the Instruction TCM incurs a single stall cycle. This is because the memory requires that the write address is pipelined to be in-line with the write data. The read address cannot then be applied until the next cycle, so requiring the stall. Figure 5.4 shows this sequence.

Figure 5.4. Data write followed by data read of Instruction TCM

Figure 5.4. Data write followed by data read
of Instruction TCM

Similarly, a data write operation followed by an instruction fetch incurs a stall cycle, as shown in Figure 5.5.

Figure 5.5. Data write followed by instruction fetch of Instruction TCM

Figure 5.5. Data write followed by instruction
fetch of Instruction TCM

A data read followed by an instruction fetch also requires a stall cycle. This stall is incurred as a result of the multiplexor switching being controlled by registered versions of the ARM9E-S data memory interface. The stall is therefore inserted for the data read cycle rather than the instruction read. Figure 5.6 shows the sequence.

Figure 5.6. Data read followed by instruction fetch

Figure 5.6. Data read followed by instruction
fetch

Simultaneous instruction fetch and data write incurs a single stall cycle because of the pipelining of the data access to the data address. Figure 5.7 shows the sequence.

Figure 5.7. Simultaneous instruction fetch and data write

Figure 5.7. Simultaneous instruction fetch and
data write

A data write followed by a simultaneous instruction fetch and data read incurs two stall cycles. The first stall is caused by the write still being active when the instruction fetch begins. The second stall is caused by the two reads required. This is shown in Figure 5.8.

Figure 5.8. Data write followed by simultaneous instruction fetch and data read

Figure 5.8. Data write followed by simultaneous
instruction fetch and data read