You copied the Doc URL to your clipboard.
Table A.1 describes the common AMBA AHB signals.
Signal name | Type | Source/ destination | Description |
|---|---|---|---|
nHCLK | Input | Clock control | Inverted bus clock input. It is used only for the generation of the write enable output. |
HCLK | Input | Clock control | Bus clock input, that times all bus transfers. All signal timings are related to the rising edge. |
HRESETn | Input | Reset controller | Bus reset input, active LOW, used to reset the system and the bus when asserted LOW. |
HREADYIN | Input | Other AHB slaves | Transfer completed input. When HIGH the HREADYIN signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. |